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maxim integrated products 1 some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sal es channels. for information about device errata, go to: www.maxim-ic.com/errata . for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim-ic.com. DS33X162/ds33x161/ds33x82/ds33x81/ ds33x42/ds33x41/ds33x11/ds33w41/ds33w11 ethernet over pdh mapping devices general description the DS33X162 family of semiconductor devices extend 10/100/1000mbps ethernet lan segments by encapsulating mac frames in gfp-f, hdlc, chdlc, or x.86 (laps) for transmission over pdh/tdm data streams. the devices suppor t the ethernet over pdh (eopdh) standards for t he delivery of ethernet access services, including elan, eline, and vlan. the multiport devices support vcat/lcas for dynamic link aggregation. t he serial links support bidirectional synchronous interconnect up to 52mbps over xdsl, t1/e1/j1, t3/e3, or v.35/optical. the devices perform store-and-forward of frames with ethernet traffic conditioning and bridging functions at wire speed. the programmability of classification, priority queuing, encapsulation, and bundling allows great flexibility in providing various ethernet services. oam flows can be extracted and inserted by an external processor to manage the ethernet service. the voice ports of the ds33w41 and ds33w11 easily connect to external codecs for integrated voice and data service applications. applications bonded transparent lan service lan extension ethernet delivery over t1/e1/j1, t3/e3, oc-1/ec-1, g.shdsl, or hdsl2/4 functional diagram features ? 10/100/1000 ieee 802.3 mac (mii/rmii/gmii) with autonegotiation and flow control ? gfp-f/laps/hdlc/chdlc encapsulation ? vcat/lcas link aggregation for up to 16 links ? supports up to 200ms differential delay ? quality of service (qos) support ? vlan, q-in-q, 802.1p, and dscp support ? ethernet bridging and filtering ? add/drop oam frames from p interface ? traffic shaping through cir/cbs policing ? external 256mb, 125mhz ddr sdram buffer ? parallel and spi? microprocessor interfaces ? 1.8v, 2.5v, 3.3v supplies ? ieee 1149.1 jtag support features continued in section 2 . ordering information ports part tdm ethernet voice pin- package DS33X162+ 16 2 0 256 csbga ds33x161+ 16 1 0 256 csbga ds33x82+ 8 2 0 256 csbga ds33x81+ 8 1 0 256 csbga ds33x42+ 4 2 0 256 csbga ds33x41+ 4 1 0 256 csbga ds33x11+ 1 1 0 144 csbga ds33w41+ 4 1 1 256 csbga ds33w11+ 1 1 1 256 csbga note: all devices are specified over the -40 c to +85 c industrial operating temperature range. + denotes a lead-free/rohs-compliant package. spi is a trademark of motorola, inc. rev: 063008 sdram controller macs enet phys processor ddr sdram tdm liu/ framer traffic mgmt bridging 8-bit & spi p interface qos policy buffer manager gfp/ laps/ hdlc voice port wan serial ports clad DS33X162
_________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 2 of 375 table of contents 1. detailed description ........................................................................................................... ... 9 2. feature highlights............................................................................................................. ... 10 2.1 g eneral ............................................................................................................................... ....... 10 2.2 vcat/lcas l ink a ggregation (i nverse m ultiplexing ) .......................................................... 10 2.3 hdlc........................................................................................................................... ................ 10 2.3.1 chdlc.......................................................................................................................... ........................ 10 2.4 gfp-f.......................................................................................................................... ................ 11 2.5 x.86 s upport ............................................................................................................................. 11 2.6 ddr sdram i nterface ............................................................................................................. 11 2.7 mac i nterfaces ......................................................................................................................... 11 2.7.1 ethernet bridgi ng for 10/100 ................................................................................................... ............. 12 2.7.2 ethernet traffic classification ................................................................................................ .............. 12 2.7.3 ethernet bandwi dth policing .................................................................................................... ............ 12 2.7.4 ethernet traffic scheduling.................................................................................................... .............. 12 2.7.5 connection endpoint s ........................................................................................................... ............... 12 2.7.6 virtual co nnection............................................................................................................. ................... 12 2.7.7 connection and aggregation ..................................................................................................... .......... 12 2.7.8 ethernet control fr ame processing.............................................................................................. ....... 12 2.7.9 q-in-q ......................................................................................................................... ......................... 12 2.8 s erial p orts .............................................................................................................................. 13 2.8.1 voice po rts.................................................................................................................... ....................... 13 2.9 m icroprocessor i nterface ...................................................................................................... 13 2.10 s lave s erial p eripheral i nterface (spi) f eatures ............................................................ 13 2.11 t est and d iagnostics ............................................................................................................. 13 2.12 s pecifications c ompliance .................................................................................................... 13 3. applicable equipment types.............................................................................................. 14 4. acronyms & glossary .......................................................................................................... 17 5. designing with the DS33X162 family of devices.......................................................... 18 5.1 i dentification of a pplication r equirements .......................................................................... 18 5.2 d evice s election ....................................................................................................................... 18 5.3 a ncillary d evice s election ...................................................................................................... 19 5.4 c ircuit d esign ............................................................................................................................ 19 5.5 b oard l ayout ............................................................................................................................. 19 5.6 s oftware d evelopment ............................................................................................................ 19 6. block diagrams ................................................................................................................. ..... 20 7. pin descriptions ............................................................................................................... ....... 21 7.1 p in f unctional d escription ...................................................................................................... 21 8. functional description ....................................................................................................... 34 8.1 p arallel p rocessor i nterface ................................................................................................ 35 8.1.1 read-write/data strobe modes................................................................................................... ........ 35 8.1.2 clear on read .................................................................................................................. .................... 35 8.1.3 interrupt and pin modes........................................................................................................ ............... 35 8.1.4 multiplexed bu s operation...................................................................................................... ............. 35 8.2 spi s erial p rocessor i nterface ............................................................................................. 36 8.3 c lock s tructure ....................................................................................................................... 37 8.3.1 serial interfac e clock modes ................................................................................................... ............ 39 8.3.2 ethernet interfac e clock modes................................................................................................. .......... 39
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 3 of 375 8.4 r esets and l ow -p ower m odes ................................................................................................ 39 8.5 i nitialization and c onfiguration .............................................................................................. 41 8.6 g lobal r esources .................................................................................................................... 41 8.7 p er -p ort r esources ................................................................................................................ 41 8.8 d evice i nterrupts ..................................................................................................................... 41 8.9 f orwarding m odes and wan c onnections ............................................................................ 43 8.9.1 forwarding modes ............................................................................................................... ................ 43 8.9.2 wan conn ections................................................................................................................ ................ 49 8.9.3 queue confi guration ............................................................................................................ ................ 50 8.10 b andwidth c apabilities (t hroughput ).................................................................................. 51 8.11 s erial (wan).......................................................................................................................... . 52 8.11.1 voice support (ds33w 11 and dw33w 41 only)................................................................................. 52 8.12 l ink a ggregation and l ink c apacity a djustment (vcat/lcas) ........................................ 53 8.12.1 vcat/lcas control frame for t3/e3 .............................................................................................. ... 54 8.12.2 vcat/lcas configurat ion and operation.......................................................................................... . 55 8.12.3 link capacity adjust ment scheme (lcas) ......................................................................................... 56 8.12.4 alarms and conditions re lated to vc at/lcas.................................................................................... 57 8.13 a rbiter /b uffer m anager ....................................................................................................... 57 8.14 f low c ontrol ......................................................................................................................... 58 8.14.1 full duplex fl ow cont rol....................................................................................................... ................ 59 8.14.2 half duplex fl ow cont rol ....................................................................................................... ............... 59 8.15 e thernet i nterfaces ............................................................................................................. 60 8.15.1 gmii mode ...................................................................................................................... ..................... 62 8.15.2 mii mode ....................................................................................................................... ....................... 63 8.15.3 dte and dc e mode ............................................................................................................... ............. 65 8.15.4 rmii mode...................................................................................................................... ...................... 66 8.16 q uality of s ervice (q o s) f eatures ..................................................................................... 67 8.16.1 vlan forwarding by vid (i eee 802.1q) ........................................................................................... .. 67 8.16.2 programming the vl an id table .................................................................................................. ...... 68 8.16.3 priority coding with vlan tags (ieee 802.1p)................................................................................... 69 8.16.4 priority coding with mult iple (q-in-q) vlan tags............................................................................... 70 8.16.5 priority coding with dscp ...................................................................................................... ............. 71 8.16.6 programming the pr iority table ................................................................................................. .......... 72 8.17 oam support with f rame t rapping , e xtraction , and i nsertion ....................................... 74 8.17.1 frame tr apping................................................................................................................. ................... 76 8.17.2 frame extraction and frame insertion ........................................................................................... ..... 77 8.17.3 oam by ethernet dest ination address (da)....................................................................................... . 78 8.17.4 oam by ip address.............................................................................................................. ................ 78 8.17.5 oam by vl an tag................................................................................................................ ............... 78 8.17.6 snmp s upport ................................................................................................................... .................. 78 8.18 b ridging and f iltering ........................................................................................................... 79 8.18.1 bridge filter table re set ...................................................................................................... ............... 79 8.19 e thernet mac ........................................................................................................................ 80 8.19.1 phy mii management block and mdio in terface ............................................................................... 83 8.19.2 ethernet mac management c ounters for rf c2819 rmon ............................................................... 84 8.19.3 programmable ethernet desti nation address filtering........................................................................ 85 8.20 e thernet f rame e ncapsulation ........................................................................................... 86 8.20.1 transmit packet proces sor (encapsulator) ....................................................................................... .. 86 8.20.2 receive packet proces sor (decap sulator) ........................................................................................ .. 87 8.20.3 gfp-f encapsulation and decapsul ation.......................................................................................... .. 89 8.20.4 x.86 encoding and dec oding ..................................................................................................... ......... 94 8.20.5 hdlc encoding and deco ding ..................................................................................................... ....... 96 8.20.6 chdlc encoding and decoding.................................................................................................... ...... 98 8.21 cir/cbs c ontroller ............................................................................................................. 99 9. applications information................................................................................................. 101
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 4 of 375 9.1 i nterfacing to m axim t1/e1 t ransceivers ............................................................................ 101 9.2 i nterfacing to m axim t3/e3 t ransceivers ............................................................................ 103 10. device registers............................................................................................................... .... 105 10.1 r egister b it m aps ................................................................................................................ 106 10.1.1 global register bit map ........................................................................................................ ............. 106 10.1.2 mac indirect regi ster bit map.................................................................................................. ......... 131 10.2 g lobal r egister d efinitions ............................................................................................... 141 10.2.1 microport re gisters ............................................................................................................ ................ 147 10.2.2 mac 1 interface ac cess registers ............................................................................................... ..... 152 10.2.3 mac 2 interface ac cess registers ............................................................................................... ..... 156 10.2.4 vlan control registers ......................................................................................................... ............ 160 10.3 e thernet i nterface r egisters ........................................................................................... 164 10.3.1 wan extraction and transm it lan r egisters..................................................................................... 164 10.3.2 receive lan regist er defi nitions............................................................................................... ....... 175 10.3.3 bridge filter regist ers........................................................................................................ ................ 188 10.4 a rbiter r egisters ................................................................................................................ 189 10.4.1 arbiter register bit descriptions .............................................................................................. .......... 189 10.5 p acket p rocessor (e ncapsulator ) r egisters ................................................................. 230 10.6 d ecapsulator r egisters .................................................................................................... 236 10.7 vcat/lcas r egisters ......................................................................................................... 245 10.7.1 transmit vcat registers ........................................................................................................ .......... 245 10.7.2 vcat receive regist er description .............................................................................................. .... 252 10.8 s erial i nterface r egisters ................................................................................................ 265 10.8.1 serial interface transm it and common regist ers............................................................................. 265 10.8.2 serial interface transmit register bit descriptions ........................................................................... 265 10.8.3 transmit per serial port register description .................................................................................. . 269 10.8.4 transmit voice port r egister description ....................................................................................... ... 270 10.8.5 receive per serial port register description ................................................................................... . 273 10.8.6 receive voice port r egister description ........................................................................................ ... 274 10.8.7 mac regi sters .................................................................................................................. ................. 275 11. functional timing .............................................................................................................. ... 330 11.1 f unctional spi i nterface t iming ........................................................................................ 330 11.1.1 spi transmission format and cpha polarity ................................................................................... 330 11.2 f unctional s erial i nterface t iming ................................................................................... 333 11.3 v oice p ort f unctional t iming d iagrams ............................................................................ 335 11.4 mii/rmii and gmii i nterfaces .............................................................................................. 336 12. operating parameters ...................................................................................................... 339 12.1 t hermal c haracteristics .................................................................................................... 341 12.2 t ransmit and r eceive gmii i nterface ................................................................................ 342 12.3 t ransmit and r eceive mii i nterface ................................................................................... 344 12.4 t ransmit and r eceive rmii i nterface ................................................................................ 346 12.5 mdio i nterface .................................................................................................................... 348 12.6 t ransmit and r eceive wan i nterface ................................................................................ 349 12.7 t ransmit and r eceive v oice p ort i nterface ..................................................................... 351 12.8 ddr sdram i nterface ........................................................................................................ 353 12.9 ac c haracteristics ?m icroprocessor b us i nterface t iming ........................................ 355 12.10 jtag i nterface .................................................................................................................... 362 13. jtag information ............................................................................................................... ... 363 13.1 jtag tap c ontroller s tate m achine d escription ......................................................... 364 13.1.1 tap controller state machine ................................................................................................... ........ 364 13.2 i nstruction r egister ........................................................................................................... 367 13.2.1 sample:preload ................................................................................................................. ......... 367
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 5 of 375 13.2.2 bypass ......................................................................................................................... .................... 367 13.2.3 extest ......................................................................................................................... .................... 367 13.2.4 clamp.......................................................................................................................... ..................... 367 13.2.5 highz .......................................................................................................................... ...................... 367 13.2.6 idcode ......................................................................................................................... .................... 367 13.3 jtag id c odes ...................................................................................................................... 368 13.4 t est r egisters ..................................................................................................................... 368 13.4.1 boundary scan register ......................................................................................................... ........... 368 13.4.2 bypass register ................................................................................................................ ................. 368 13.4.3 identificati on regi ster........................................................................................................ ................. 368 13.5 jtag f unctional t iming ...................................................................................................... 369 14. pin configuration .............................................................................................................. .. 370 14.1 DS33X162/x161/x82/x81/x42/x41 p in c onfiguration ?256-b all csbga....................... 370 14.2 ds33w41/ds33w11 p in c onfiguration ?256-b all csbga ............................................. 371 14.3 ds33x11 p in c onfiguration ?144-b all csbga................................................................ 372 15. package information ......................................................................................................... 373 15.1 256-b all csbga, 17 mm x 17 mm (56-g6017-001) ................................................................. 373 15.2 144-b all csbga, 10 mm x 10 mm (56-g6008-003) ................................................................. 374 16. document revision history .............................................................................................. 375
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 6 of 375 list of figures figure 3-1. standardized ethernet trans port over multiple t1/e1 lines .......................................................... ........ 14 figure 3-2. standardized ethernet tran sport over a si ngle t1/e 1 line ........................................................... ........ 15 figure 3-3. remote ip dslam t1/e1 trunk card ................................................................................... ................. 16 figure 6-1. simplified logical block diagram................................................................................... ......................... 20 figure 7-1. 256-ball, 17mm x 17mm csbga pinout (DS33X162/x161/ x82/x81/x42/x41) .................................... 31 figure 7-2. 256-ball, 17mm x 17mm csbga pinout (ds3 3w41/ds33w11) ........................................................... 32 figure 7-3. 144-ball, 10mm x 10 mm, csbga pinout (ds33x11) ...................................................................... ...... 33 figure 8-1. cloc king diagram ................................................................................................... ................................. 38 figure 8-2. device interrupt information fl ow diagram .......................................................................... .................. 42 figure 8-3. forwarding mode 1: single ethernet port wi th priority forwar ding ................................................... ..... 44 figure 8-4. forwarding mode 2: one or two et hernet port forwardi ng with sc heduling......................................... 45 figure 8-5. forwarding mode 3: single ethernet port wi th lan-vlan forwarding.................................................. 46 figure 8-6. forwarding mode 4: 1 ethernet port with port id and lan-vlan forwarding....................................... 47 figure 8-7. forwarding mode 5: full lan-to-wan and wan- to-lan vlan forwarding ......................................... 48 figure 8-8. ieee 802. 3 ethernet frame .......................................................................................... .......................... 60 figure 8-9. example conf iguration of gmii interf ace (dte mo de only)............................................................ ....... 62 figure 8-10. example configuration as dte connected to an ethernet phy in mii mode ....................................... 63 figure 8-11. example configurat ion as a dce in mii mode ........................................................................ ............. 65 figure 8-12. rmii interfac e (dte mode only).................................................................................... ....................... 66 figure 8-13. ieee 802.1q and 802.1p fiel d form at ............................................................................... .................. 69 figure 8-14. vlan q- in-q fiel d format.......................................................................................... .......................... 70 figure 8-15. differentiated services co de point (dscp) head er information...................................................... .... 71 figure 8-16. supported trappe d ethernet fr ame types ............................................................................ .............. 75 figure 8-17. mii management frame .............................................................................................. .......................... 83 figure 8-18. gfp-f null en capsulated frame format .............................................................................. ............ 91 figure 8-19. gfp-f linear extensi on encapsulated frame format................................................................. 93 figure 8-20. laps / x.86 enca psulated frame format ............................................................................. ............... 94 figure 8-21. hdcl encaps ulated fram e format.................................................................................... .................. 97 figure 8-22. chdlc enca psulated fram e format ................................................................................... ................. 98 figure 9-1. interfacing wi th t1/e1 transceivers................................................................................ ...................... 101 figure 9-2. example functional timing: ds 2155 e1 transmit-sid e boundary timing .......................................... 101 figure 9-3. example functional timing: ds 2155 t1 transmit-sid e boundary timing........................................... 102 figure 9-4. example functional timing: ds2155 e1 receive-si de boundary timing ........................................... 102 figure 9-5. example functional timing: ds2155 t1 receive-si de boundary timing............................................ 102 figure 9-6. interfacing wi th t3/e3 transceivers................................................................................ ...................... 103 figure 9-7. example functional timing: ds 3170 ds3 transmit-sid e boundary timing........................................ 103 figure 9-8. example functional timing: ds 3170 ds3 receive-side boundary timing......................................... 104 figure 11-1. spi serial port access fo r read mode, spi_cpol= 0, spi_cpha = 0 ............................................ 330 figure 11-2. spi serial port access fo r read mode, spi_cpol = 1, spi_c pha = 0 .......................................... 330 figure 11-3. spi serial port access fo r read mode, spi_cpol = 0, spi_c pha = 1 .......................................... 331 figure 11-4. spi serial port access fo r read mode, spi_cpol = 1, spi_c pha = 1 .......................................... 331 figure 11-5. spi serial port access for write mode, spi_cpol = 0, spi_cpha = 0 .......................................... 331 figure 11-6. spi serial port access for write mode, spi_cpol = 1, spi_cpha = 0 .......................................... 331 figure 11-7. spi serial port access for write mode, spi_cpol = 0, spi_cpha = 1 .......................................... 332 figure 11-8. spi serial port access for write mode, spi_cpol = 1, spi_cpha = 1 .......................................... 332 figure 11-9. transmit serial po rt interface, without vcat ...................................................................... ............... 333 figure 11-10. transmit serial port interfac e with vcat ......................................................................... ................ 333 figure 11-11. transmit serial port interface, with gapped clock ................................................................ ........... 333 figure 11-12. transmit serial port interf ace with vcat, early tsync (2 cycles)................................................. . 334 figure 11-13. receive serial port interf ace, without vcat, rising edge sampling ................................................ . 334 figure 11-14. receive serial port inte rface with vcat, ri sing edge sa mpling .................................................... ... 334 figure 11-15. receive serial port interface with g apped clock (t1) ............................................................. ........ 334 figure 11-16. transmit voice port interface with pcm octets.................................................................... ............ 335 figure 11-17. receive voice port interface with pcm octets..................................................................... ............ 335 figure 11-18. gmii transmit inte rface function al timing ........................................................................ ............... 336
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 7 of 375 figure 11-19. gmii receive inte rface functio nal timing ......................................................................... ............... 336 figure 11-20. mii transmi t functional timing................................................................................... ...................... 337 figure 11-21. mii transmit half duplex with a collision f unctional timing ...................................................... ...... 337 figure 11-22. mii receiv e functional timing.................................................................................... ...................... 337 figure 11-23. rmii transmit in terface functi onal timing ........................................................................ ............... 338 figure 11-24. rmii receive inte rface functio nal timing ......................................................................... ............... 338 figure 12-1. transmit gm ii interfac e timing.................................................................................... ....................... 342 figure 12-2. receive gm ii interfac e timing..................................................................................... ....................... 343 figure 12-3. transmit mii interfac e timing ..................................................................................... ........................ 344 figure 12-4. receive m ii interfac e timing ...................................................................................... ........................ 345 figure 12-5. transmit rm ii interfac e timing.................................................................................... ....................... 346 figure 12-6. receive rm ii interfac e timing..................................................................................... ....................... 347 figure 12-7. mdio interface timing ............................................................................................. ........................... 348 figure 12-8. transmit wan timing (noninve rted tclk) ............................................................................ ............ 349 figure 12-9. receive wan ti ming (noninve rted rclk) ............................................................................. ........... 350 figure 12-10. transmit voic e port interf ace timing............................................................................. ................... 351 figure 12-11. receive voice port interface timing.............................................................................. ................... 352 figure 12-12. ddr sdra m interfac e timing....................................................................................... ................... 354 figure 12-13. intel bus read timing (mode = 0) ................................................................................. ................. 356 figure 12-14. intel bus wri te timing (mode = 0)................................................................................ ................... 356 figure 12-15. motorola bus read timing (mode = 1) .............................................................................. ............. 357 figure 12-16. motorola bus write timing (mode = 1) ............................................................................. .............. 357 figure 12-17. multiplexed intel bus read timi ng (mode = 0) ..................................................................... .......... 359 figure 12-18. multiplexed intel bus write timi ng (mode = 0) .................................................................... ........... 359 figure 12-19. multiplexed motorola bus read timing (mode = 1) .................................................................. ...... 360 figure 12-20. multiplexed motorola bus write timi ng (mode = 1) ................................................................. ....... 360 figure 12-21. spi interf ace timing diagram ..................................................................................... ...................... 361 figure 12-22. jtag interface timing ............................................................................................ .......................... 362 figure 13-1. jtag functi onal block diagram ..................................................................................... .................... 363 figure 13-2. tap contro ller state diagram...................................................................................... ....................... 366 figure 13-3. jtag fu nctional timing............................................................................................ .......................... 369
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 8 of 375 list of tables table 1-1. product selection matrix............................................................................................ ................................. 9 table 7-1. detailed pin descriptions ........................................................................................... .............................. 21 table 8-1. clocking options fo r the ethernet interface ......................................................................... .................... 37 table 8-2. software reset functions ............................................................................................ ............................ 39 table 8-3. block enable func tions .............................................................................................. .............................. 40 table 8-4. forwarding mode s supported by device ................................................................................ ................. 49 table 8-5. maximum number of t3/e3 lines per encapsulator (ds 33x162 and ds33x82 only) .......................... 51 table 8-6. vcat/lcas c ontrol frame for t1/e1................................................................................... ................... 53 table 8-7. vcat/lcas c ontrol frame for t3/e3................................................................................... ................... 54 table 8-8. configuration recommen dations for maxi mum fram e length.............................................................. .. 61 table 8-9. selection of mac interface modes for port 1 ......................................................................... .................. 61 table 8-10. selection of mac interface modes for port 2........................................................................ ................. 61 table 8-11. m ii mode op tions ................................................................................................... ................................ 64 table 8-12. example priority table configurat ion for dscp ...................................................................... .............. 72 table 8-13. example priority table configurat ion for pcp ....................................................................... ................ 73 table 8-14. mac co ntrol registers.............................................................................................. ............................. 81 table 8-15. mac st atus registers ............................................................................................... ............................. 81 table 8-16. mac co unter registers.............................................................................................. ............................ 82 table 8-17. gfp type/thec fiel d (payload header ) defini tion .................................................................... ........... 89 table 8-18. gfp upi definitions ................................................................................................ ............................... 89 table 8-19. example gf p type + thec values ..................................................................................... .................. 90 table 8-20. gfp cid/spare/ehec (e xtension header) fi eld defi nition............................................................. ...... 92 table 8-21. example cid + spare + ehec values.................................................................................. ................. 92 table 8-22. credit threshold setti ngs with result ing bandwidths................................................................ .......... 100 table 10-1. regist er address map ............................................................................................... ........................... 105 table 10-2. global r egister bit map............................................................................................ ............................ 106 table 10-3. mac indirect register bit map ...................................................................................... ....................... 131 table 10-4. defaul t gl.idr values .............................................................................................. ........................... 141 table 10-5. valid condi tions for mp l > 2048.................................................................................... ...................... 182 table 12-1. recommended dc operating conditions ................................................................................ ............ 339 table 12-2. dc electric al characteristics...................................................................................... .......................... 340 table 12-3. thermal characteristics............................................................................................ ............................ 341 table 12-4. transmit gmii interface............................................................................................ ............................ 342 table 12-5. receiv e gmii interface............................................................................................. ............................ 343 table 12-6. transmit mii interface............................................................................................. .............................. 344 table 12-7. receiv e mii interface.............................................................................................. .............................. 345 table 12-8. transmit rmii interface ............................................................................................ ............................ 346 table 12-9. receiv e rmii interface ............................................................................................. ............................ 347 table 12-10. md io interface .................................................................................................... ............................... 348 table 12-11. transm it wan interface ............................................................................................ ......................... 349 table 12-12. receiv e wan inte rface ............................................................................................. ......................... 350 table 12-13. transmit voice port interface..................................................................................... ........................ 351 table 12-14. receive vo ice port interface...................................................................................... ........................ 352 table 12-15. ddr sdram interface............................................................................................... ........................ 353 table 12-16. parallel microprocessor bus....................................................................................... ........................ 355 table 12-17. multiplex ed microproce ssor bus .................................................................................... .................... 358 table 12-18. spi micr oprocessor bus mode....................................................................................... .................... 361 table 12-19. jtag interface .................................................................................................... ............................... 362 table 13-1. instruct ion codes for ieee 1149.1 archit ecture..................................................................... .............. 367 table 13-2. id code structure.................................................................................................. ............................... 368
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 9 of 375 1. detailed description the DS33X162 family of devices provide interconnecti on and mapping functionality between ethernet systems and wan time-division multiplexed (tdm) systems such as t1/e1/j1, hdsl, t3/e3, and sonet/sdh. the device is composed of up to two 10/100/1000 ethernet macs, up to 16 serial ports, a arbite r, gfp-f /hdlc/chdlc/x.86 (laps) mappers, a ddr sdram interface, and control ports. ethernet traffi c is encapsulated with gfp-f, hdlc, chdlc, or x.86 (laps) to be transmitted over the wan seri al interfaces. the wan serial interfaces also receive encapsulated ethernet frames and transmit the extracted fr ames over the ethernet port s. the lan frame interface consists of ethernet interfaces using one of two physical layer protocols. it can be configured with up to two 10/100mbps mii/rmii ports or a single gbe gmii port. the wan serial interface can be configured for up to eight serial data streams at up to 52mbps each, or 16 serial data streams at up to 2.5mbps each. the serial interfaces can be seamlessly connected to the maxim t1/e1/j1 fr amers, line interface units (lius), and single-chip transceivers (scts). the wan interfaces can also be seamlessly connected to the maxim t3/e3/sts-1 framers, lius, and scts to provide t3, e3, or sts1 connectivity. microprocessor control can be accomplished through a 8-bit micro controller port or spi bus. the device has a 125mhz ddr sdram controller and interfaces to a 32-bit wide 256mb ddr sdram via a 16-bit data bus. the ddr sdram is used to buffer data from the ethernet and wan ports for transport. the power supplies consist of a 1.8v core supply, a 2.5v ddr sdram supply, and 3.3v i/o supply. the ddr interface also requires a 1.25v reference voltage that can be obtained through a resistor-divider network. table 1-1. product selection matrix ordering number ethernet ports tdm ports voice ports vlan forwarding support supported forwarding modes wan groups (vcgs) p control package ds33x11+ 1 10/100/gbe 1 0 no 2 1 spi 10mm 144 csbga ds33w11+ 1 10/100/gbe 1 1 no 2 1 spi or parallel 17mm 256 csbga ds33x41+ 1 10/100/gbe 4 0 no 2 1 spi or parallel 17mm 256 csbga ds33w41+ 1 10/100/gbe 4 1 no 1, 2, 3 1 & 3 spi or parallel 17mm 256 csbga ds33x42+ 2 10/100 or 1 gbe 4 0 yes 1, 2, 3, 5 1 & 3 spi or parallel 17mm 256 csbga ds33x81+ 1 10/100/gbe 8 0 no 2 1 spi or parallel 17mm 256 csbga ds33x82+ 2 10/100 or 1 gbe 8 0 yes 1, 2, 3, 4, 5 1, 2, 3, 4 spi or parallel 17mm 256 csbga ds33x161+ 1 10/100/gbe 16 0 no 2 1 spi or parallel 17mm 256 csbga DS33X162+ 2 10/100 or 1 gbe 16 0 yes 1, 2, 3, 4, 5 1, 2, 3, 4 spi or parallel 17mm 256 csbga
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 10 of 375 2. feature highlights 2.1 general ? 17mm 256 pin csbga package (ds33x 162/x161/x82/x81/x41/w41/w11) ? 10mm 144 pin csbga package (ds33x11) ? 1.8v, 2.5v, 3.3v supplies ? ieee 1149.1 jtag boundary scan ? software access to devic e id and silicon revision ? development support includes evaluation kit, dr iver source code, and reference designs 2.2 vcat/lcas link aggregation (inverse multiplexing) ? link aggregation for up to 16 links per itu-t g.7043/g.7042 ? up to 16 members per vcg ? 4 vcgs for the DS33X162/x82, 2 vcgs for the ds33x42, 1 vcg for t he ds33x161/x81/x41/w41 ? differential delay compensation for up to 200 ms among members of a vcg ? receive and transmit are i ndependent (asymmetry support) ? user programmable configuration of wan ports used for vcg ? supports virtual concatenation of up to 8 t3/e3 or 16 t1/e1 ? vcat/lcas link aggregation not available in the ds33x11 and ds33w11 2.3 hdlc ? up to 4 hdlc controller engines ? compatible with polled or interrupt driven environments ? supports bit stuffing/destuffing wit hout address/control/pid fields ? programmable fcs insertion and extraction, with removal of payload fcs ? 16-bit or 32-bit fcs, with support for fcs error insertion ? programmable frame size limits (minimum 64 bytes and maximum 2016 bytes) ? selectable self-synchronizing x 43 +1 frame scrambling/descrambling ? separate valid and invalid frame counters ? programmable inter-frame fill for transmit hdlc ? supports transparency proc essing and abort sequence ? programmable frame filtering for fcs erro rs, aborts, or frame length errors 2.3.1 chdlc ? bit stuffing with address/control/pid/fcs fields ? programmable interframe fill length. ? transparency processing ? counters: number of received valid frames and erred frames ? incoming frame discard due to fcs error, abort or frame length longer than preset max. ? the default maximum frame length is associated with the maximum pdu length of mac frame ? extract slarp for external processor interpretation
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 11 of 375 2.4 gfp-f ? gfp frame mode per itu-t g.7041 ? gfp idle frame insertion and extraction ? supports null and linear headers ? chec based frame delineation ? x 43 +1 payload and barker sequence scrambling/descrambling ? csf frame generation and detection ? error detection over core header and type headers ? programmable crc-32 generation and verification 2.5 x.86 support ? encapsulation per itu-t x.86 (l ink a ccess p rocedure for s onet/sdh), with 32 bit fcs ? transmit transparency processing - 7e is replaced by 7d, 5e ? transmit transparency processing ? 7d replaced by 7d, 5d ? receive rate adaptation (7d, dd) removal. ? receive transparency processing - 7d, 5e is replaced by 7d ? receive transparency processing ? 7d, 5d is replaced by 7d ? receive abort sequence - frame is dropped if 7d7e is detect ? selectable self-synchronizing x 43 +1 frame scrambling/descrambling ? counters: number of received valid frames and erred frames ? frame filtering due to bad addres s/control/sapi, fcs error, abort, or frame length errors 2.6 ddr sdram interface ? 16-bit wide data bus with dual edge transfers and auto refresh timing ? designed to interface with 256mbit jedec jesd79 d compliant ddr sdrams with a 16-bit data bus ? addressable memory range up to 256 mbits ? jesd79d compliant device sizes other than 256 mb its may be used, limited to 256 mbit utilization ? compatible with ddr266+ ? sdram interface clock output of 125mhz ? direct connection to external ddr sdram (p2p mode support) ? example devices: micron mt46v16m16, sams ung k4h561638f and hynix hy5du561622cf 2.7 mac interfaces ? two e/fe mac ports with mii/rmii or one gbe port with gmii. ? 10mbps/100mbps/1000mbps data rates ? configurable for dte or dce mode ? facilitates auto-negotiation by host microprocessor ? programmable half and full-duplex modes ? flow control per 802.3 half-duplex (back- pressure) and full-duplex (pause) modes ? auto negotiation for rates and duplex modes ? programmable max mac frame lengths up to 2016 bytes for e/fe, 12kb for gbe. ? minimum mac frame length: 64 bytes ? discards frames larger than the max mac frame size , runt, non-octet bounded, or bad-fcs frames upon reception ? programmable threshold for sdram queues to init iate flow control, with status indication ? terminal and facility loopbacks at mac port (without sa/da swapping) ? ethernet management interface (mdio) ? supports all applicable rmon (rfc2819) 32 bit counters with saturation at max count. ? configurable for promiscuous mode and broadcast-discard mode.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 12 of 375 2.7.1 ethernet bridging for 10/100 ? 4k address and vlan id lookup table for learning and filtering ? programmable aging between 1 to 300 seconds in 1 second intervals 2.7.2 ethernet tra ffic classification ? ingress classification according to ethernet cos ? programmable class map to 4 queues for each ethernet port 2.7.3 ethernet bandwidth policing ? bandwidth policing with programmable ci r/cbs on ethernet ingress direction. ? bandwidth policing based on a per port basis. ? programmable ieee 802.3 pause flow c ontrol or discard based on cir/cbs ? programmable non-conforming ethernet frame discard based on cir/cbs ? see section 8.21 for details on the granularity of cir/cbs. 2.7.4 ethernet traffic scheduling ? programmable scheduler for etherne t flows toward pdh port(s): o strict priority, or o weighted queuing 2.7.5 connection endpoints ? connection between ethernet port(s) and serial(s) based on ? ethernet side: o per ethernet port, or o per vlan id (sub-interface) o priority (vlan pcp or dscp) ? wan side (serial): o per serial port, or o per vcg bundle 2.7.6 virtual connection ? each connection configured for bi-directi onal flow with selected encapsulation. 2.7.7 connection and aggregation ? forwarding between endpoints based on the following options: o per ethernet port per serial port or per vcg o per vlan id per serial port or port vcg ? vlan forwarding supported only in the ds33x42, ds33x82, and DS33X162 2.7.8 ethernet control frame processing ? control frames, except pause and oam, shall be forwarded without processing. ? pause and oam frames can be programmed to be intercepted, discarded or forwarded. 2.7.9 q-in-q ? programmable carrier vlan tag insertion.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 13 of 375 2.8 serial ports ? four, eight or sixteen serial ports with sy nchronous clock/data at 128kbps to 52mhz. ? independently clock inputs for rx and tx operations on the per port bases. ? input clock supports either continuous or gapped clock ? seamless interconnect with maxim liu/framer/t ransceiver devices for t1/e1/j1, and t3/e3 ? terminal and facility loopbacks per port 2.8.1 voice ports ? the ds33w41 supports up to four voice ports; ds33w11 supports one voice port ? each voice port supports up to 16 ds0s of voice to be multiplexed with ethernet traffic ? devices supporting voice input are re stricted to t1/e1 wan data rates 2.9 microprocessor interface ? selectable 8-bit parallel or spi serial data bus ? multiplexed/non-multiplexed intel and motorola timing modes ? internal software reset and exte rnal hardware reset input pin ? global interrupt output pin 2.10 slave serial peripheral interface (spi) features ? four-signal synchronous serial data link operating in full duplex slave mode up to 10mbps ? direct connection and fully compliant to popular communication processors such as mpc8260 and microcontrollers such as m68hc11 2.11 test and diagnostics ? ieee 1149.1 support ? diagnostic loopbacks 2.12 specifications compliance the DS33X162 family of products adhere to the applic able telecommunications standards. the following list provides the specifications and relevant sections. ieee: 802.3-2002, csma/cd ac cess method and physical layer specifications. 802.1d (1998): mac bridge 802.1q (1998): virtual lans 802.1v-2001: vlan classification by protocol and port 802.1ag: ethernet oam (extract/insert support) 802.3ah: ethernet first mile (oam extract/insert support) ietf: rfc1662, ppp in hdlc-like framing rfc2615, ppp over sonet/sdh rfc2918, rmon mib (hardware counters, extract/insert support) itu-t: x.86 ethernet over laps g.707 network node interface for the synchronous digital hierarchy (sdh) g.7041 generic framing procedure (gfp) (12/2001) g.7042 lcas for vcat signal (02/2004) g.7043 vcat of pdh signals (07/2004) g.8040 gfp over pdh y.1303 framed gfp y.1323 ethernet over laps y.1731 ethernet oam (extract/insert support) ansi: t1x1/2000-0243r generic framing procedure other: rmii: industry implementation agreement fo r ?reduced mii interface,? sept 1997
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 14 of 375 3. applicable equipment types ? bonded transparent lan service ? lan extension ? ethernet delivery over t1/e1/ j1, t3/e3, xdsl, v.35/optical figure 3-1. standardized ethernet transport over multiple t1/e1 lines solution advantages: ? up to 200ms of differential delay tolerance, with vcat/lcas (itu-t g.7042/g.7043) link aggregation ? ethernet transport over up to 16 t1/e1s or 8 ds3s with qos and ethernet oam capability! ? no data path code development required! ? committed information rate (cir) controller can be used to throttle subscriber bandwidth usage! ? gfp, hdlc, laps, or chdlc encapsulation ? advanced forwarding modes allow use of vlan or priority for physical port assignment of frames DS33X162 ethernet-to-serial conversion, qos, vcat/lcas aggregation, bridging & filtering , buffering, rate matching, error detection, statistics gathering, oam extract/insert ddr sdram ds80c320 c for configuration mii, rmii, gmii 10/100/1000 ethernet 10/100/ 1000 phy e1/t1 #1 max3232e rs-232 config max809l c reset ? ? ds26521 t1/e1 sct #1 magnetics ds26521 t1/e1 sct #2 magnetics ds26521 t1/e1 sct #16 magnetics e1/t1 #2 e1/t1 #16 10/100 ethernet 10/100/ phy
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 15 of 375 figure 3-2. standardized ethernet transport over a single t1/e1 line solution advantages: ? ethernet transport over single or fractional e1/t1 with qos and ethernet oam capability! ? flexible fractional e1/t1 (nx64kbps in any ds 0s) support, using ds26521 channel blocking ? no data path code development required! ? gfp, hdlc, laps, or chdlc encapsulation ? solution extends easily to ds3/e3 ds33x11 ethernet-to-serial conversion, qos, bridging & filtering , buffering, rate matching, error detection, statistics gathering, oam extract/insert ddr sdram ds80c320 c for configuration mii, rmii, gmii 10/100/1000 ethernet 10/100/ 1000 phy e1/t1 max3232 rs-232 config max809l c reset ds26521 t1/e1 sct #1 programmable gapped clock, data, and frame sync
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 16 of 375 figure 3-3. remote ip dslam t1/e1 trunk card solution advantages: ? standards compliant ethernet transport over multiple e1/t1 links ? qos and ethernet oam capability! ? no data path code development required! ? gfp, hdlc, laps, or chdlc encapsulation ? cost-optimized ethernet transport ? solution extends easily to ds3/e3 8 aggregated t1/e1/j1s to subscribers ds33x81 ethernet-to- serial link aggregation gfp/vcat/lcas vlan, q-in-q, 10/100/gbe sdram ds80c320 c mii/ rmii/ gmii ds26528 octal t1/e1/j1 single-chip transceiver gbe transceiver 1000base-lx backplane xdsl line card xdsl line card xdsl line card xdsl line card ethernet switch / router
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 17 of 375 4. acronyms & glossary ? cle - customer located equipment. ? cos - class of service, 802.1q defined three us er priority bits in tag control info field. ? dce - data communication interface. ? dscp - diff serve code point, ietf defined six bits in the ip tos field. ? dte - data terminating interface. ? eopdh - ethernet over pdh. ethernet encapsulated in hdlc or gfp, transported via one or more pdh lines. ? eopos - ethernet transport over pdh over sonet/sdh. maintaining a pdh framing layer enables re-use of existing ethernet-over-ssonet/sdh and pdh-over-sonet /sdh equipment for delivering ethernet services. ? eos ? ethernet over sonet/sdh. ? fcs - frame check sequence. ? frame ? a layer-2 protocol data unit. (in genera l, layer 2 frames carry layer 3 packets). ? gapped clock - non-continuou s clock used to strobe the associated synchronous data at certain times. ? hdlc - high level data link control. ? lan - local area network. usually used to refer to a local ethernet segment. ? mac - media access control. lowest digital layer of protocol stack. performs framing, sequencing, and addressing. ? mii - media independent interface. one type of data bus between the physical layer (phy) and the mac. ? packet ? a layer 3 protocol data unit. ? pdh - plesiochronous digital hierarchy. the existing telephone network?s ?last mile.? primarily t1/e1 lines. ? phy - a device that interfaces an osi logical layer to a physical media (cat-5, twis ted-pair, etc.). in this document, interfaces an ethernet mac to copper or fiber. ? rmii - reduced media independent interface. ? vid- virtual lan identifier. ? vcat - virtual concatenation. used in conjunction with the link capacity adjustment scheme for transporting ethernet over bonded pdh or sdh/sonet tributaries. ? wan - wide area network. typically t1(ds1), e1, t3(ds3), e3, or xdsl.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 18 of 375 5. designing with the DS33X162 family of devices the DS33X162 family of products provi de the required flexibility and complexity to meet the needs of a very broad range of applications. although typical applications usi ng these devices are very complex and each application has a unique set of needs, most application devel opments follow a predictable set of steps: 1. identification of a pplication requirements 2. device selection 3. ancillary device identification 4. circuit design 5. board layout 6. software development 7. production 5.1 identification of application requirements the designer of an application using one of the devices in the DS33X162 product line should begin by answering several high-level questions. the solutions to these questions, in conjunction with referencing table 1-1, will lead to a proper device selection: how many and what type of tdm links are needed? how does data need to move between the various interfaces of the mapping device? what traffic prioritization methodologies will be needed? how many ethernet ports are needed? is direct multiplexing of pcm encoded voice traffic a requirement. 5.2 device selection the answer to ?how many and what type of tdm links ar e needed?? will normally narrow the selection to devices that contain at least that many port s. for example, if 16 e1 links are required, the applicable solutions are the ds33x161 and DS33X162. if 4 ds-3 links are required, the applicable solutions are the ds33x41, ds33x42, ds33x81, ds33x82, ds33x161, and DS33X162. the answer to ?how does data need to move between the various interfaces of the mapping device?? will usually further narrow the selection. the path any given frame takes through the device can be determined by the contents of the frame, the port of entry, the user configured wan connections, and the user configured forwarding mode. note that all devices in the product family allow insertio n and extraction of frames for inspection, (including itu-t y.1731 oam frames) by the host microprocessor, ba sed on a number of conditions outlined in section 8.17 if traffic flow is to be governed by vlan tag information, the choices ar e narrowed to only those devices that support vlan forwarding: ds33x42, ds33x 82, and DS33X162. if ingress traffic is to be segregated by vlan id or dscp priority into separate wan flows, the available number of wan groups in table 1-1 should be considered. several forwarding modes govern the flow of frames through the device. see table 8-4 in section 8.9 for more information.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 19 of 375 5.3 ancillary device selection all devices in the product family require an external dd r sdram for operation. the user must select a jedec jesd79d compliant ddr sdram. ddr 266 or faster may be used. the recommended size is 256 mbit (4 meg x 16 x 4 banks), although it is possible to use other sizes (see section 5.4). p2p operation is supported, and 0-ohm series termination is possible with proper pcb layout. all devices in the product family require an external mi croprocessor for configuration and status monitoring. because the DS33X162 family of devices are designed to require only a minimal amount of processor support, an inexpensive microcontroller can normally be used. in applic ations which make extensive use of the support for higher-layer protocols may require additional protocol proc essing capability, microprocessor selection can normally be determined by evaluating the management frame proces sing requirements of the particular application. all devices in the product family are designed to su pport both polled and interrupt-driven environments. microprocessor control is possible thro ugh the 8-bit parallel control port or spi slave port. more information on microprocessor control is available in section 8.1. note that the parallel bus is not available in the 144 pin ds33x11, and the spi slave port must be used for processor control. depending on the application, external pdh framers a nd lius may be required. maxim offers a broad range of framers, lius, and single-chip transceivers co mpatible with the DS33X162 family of products. the ethernet interface will normally be connected to an ex ternal ethernet phy or ethernet switch device. many commercially-available products are av ailable and will seamlessly interface with the device?s mii, rmii, or gmii options. several external clock sources are required for proper operation. see se ction 8.3 for more information. 5.4 circuit design note that all devices except the ds 33x11, ds33w11, and ds33w41 share a common footprint. this is intended to make it very easy to design a circuit that easily scales from 4 to 16 wan ports with alternate assembly boms. when designing a pcb for 4 or 8 ports, care should be tak en to tie the unused input pins for serial ports 5-16 or 9- 16 to ground. this will allow for use of the higher density device for prototype purposes. care should be taken that outputs from the DS33X162 family device t hat are present in the high-port count option but not in the low port-count option may potentially leave inputs on other devices fl oating, and should be pulled appropriately to a known voltage. the device?s ddr sdram interface is designed to use a jesd79d 256 mbit (4 meg x 16 x 4 bank) ddr sdram with a 16 bit data bus. if a larger ddr sdram must be used, the lowest 13 address lines (a0-a12) should be used, and care should be taken to ground any unused addre ss inputs on the ddr sdram. note that in such a case, only 256 mbits are addressable by the device. if a sm aller jesd79d ddr sdram is to be used (such as the 128 mbit mt46v8m16), the unused addr ess outputs should be left unconnected, and care should be taken in software to keep the starting and ending addresses of each queue within the same memory bank. in all cases, p2p operation is supported, and 0 series termination is possible with proper pcb layout. 5.5 board layout the ddr sdram interface has particularly stringent layout requirements. traces should have matched impedances, be of equal length, and s hould not have stubs. refer to the ddr sdram?s data sheet for more information. supply decoupling should be placed as close to the device as possible. 5.6 software development all devices in the product family hav e a common register set. an example initialization sequence is shown in section 8.5. software drivers and demonstration kit software are both available from maxim. go to www.maxim-ic.com/support for the latest information.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 20 of 375 6. block diagrams figure 6-1. simplified logical block diagram (mii mode) rxd[0:4] rx_clk rx_crs rx_err col1 tx_clk tx_en txd[0:4] mdc mdio tclk1 tdata1 tsync1 rclk1 rdata1 rsync1 ethernet mac1 p port ddr sdram port c s a 0-a10 d0-d7 wr r d i nt sd_udm sd_ldm sd_ldqs sd_udqs sdc s sra s sca s sw e sba[0:1] sda[0:12] sdata[0:15] sd_cl k sd_cl k sdclken jtag pin s arbiter/ buffer manager 4 x gfp/hdlc encapsulators transmit serial port 1 jtag clad (mii mode) rxd[0:4] rx_clk rx_crs rx_err col2 tx_clk tx_en txd[0:4] mdc mdio ethernet mac2 (x162/82/42) sysclki brdige/filter spi qos priority scheduling 4 x vcat/lcas add/drop oam frames 4 x gfp/hdlc decapsulators 4 x vcat/lcas transmit serial port 2 transmit serial port 16 receive serial port 1 receive serial port 2 receive serial port 16 tvdat a tvcl k tvsync tvden rvdat a rvcl k rvsync rvden voice port ( w41/w11 ) tclk2 tdata2 tsync2 tmclk4 tdata16 tmsync4 rclk2 rdata2 rsync2 rclk16 rdata16 rsync16 spi_mosi spi_miso spi_clk cir/cbs cir/cbs
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 21 of 375 7. pin descriptions 7.1 pin functional description note that all digital pins are inout pins in jtag mode. this feature increases the effe ctiveness of board level atpg patterns. table 7-1. detailed pin descriptions package pins name 256 144 type function microprocessor port a0 k10 ? i address bit 0. address bit 0 of the microprocessor interface. least significant bit. note that the parallel bus is not available in the 144 pin ds33x11, and the spi slave port mu st be used for processor control. a1 l9 ? i address bit 1. address bit 1 of the microprocessor interface. a2 k11 ? i address bit 2. address bit 2 of the microprocessor interface. a3 l10 ? i address bit 3. address bit 3 of the microprocessor interface. a4 k13 ? i address bit 4. address bit 4 of the microprocessor interface. a5 l11 ? i address bit 5. address bit 5 of the microprocessor interface. a6 k12 ? i address bit 6. address bit 6 of the microprocessor interface. a7 l12 ? i address bit 7. address bit 7 of the microprocessor interface. a8 g10 ? i address bit 8. address bit 8 of the microprocessor interface. a9 l13 ? i address bit 9. address bit 9 of the microprocessor interface. a10 g11 ? i address bit 10. address bit 10 of the microprocessor interface. d0/ spi_miso k6 j4 ioz data bit 0. bi-directional data bit 0 of the microprocessor interface. least significant bit. not driven when cs =1 or rst =0. spi_miso (spi_sel=1). spi serial data output (master-in slave-out). d1/ spi_mosi l6 k4 ioz data bit 1. bi-directional data bit 1 of the microprocessor interface. not driven when cs =1 or rst =0. spi_mosi (spi_sel=1). spi serial data input (master-out slave-in) d2/ spi_clk k7 l4 ioz data bit 2. bi-directional data bit 2 of the microprocessor interface. not driven when cs =1 or rst =0. spi_clk (spi_sel=1). spi serial clock input. d3 l7 ? ioz data bit 3. bi-directional data bit 3 of the microprocessor interface. not driven when cs =1 or rst =0. d4 k8 ? ioz data bit 4. bi-directional data bit 4 of the microprocessor interface. not driven when cs =1 or rst =0.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 22 of 375 package pins name 256 144 type function d5/ spi_swap l8 j5 ioz data bit 5. bi-directional data bit 5 of the microprocessor interface. not driven when cs =1 or rst =0. spi_swap (spi_sel=1). controls the address and data bit order of the spi interface. the r/w and b bit positions do not change. 0 = lsb is transmitted and received first. the resulting bit order is: r/w, a7, a8, a9, a10, a11, a12, a13, a0, a1, a2 , a3, a4, a5, a6, burst, d0, d1, d2 , d3, d4, d5, d6, d7... 1 = msb is transmitted and received first. the resulting bit order is: r/w, a13, a12, a11, a10, a9, a8, a7, a6, a5, a4 , a3, a2, a1, a0, burst, d7, d6, d5 , d4, d3, d2, d1, d0? d6/ spi_cpha k9 k5 ioz data bit 6. bi-directional data bit 6 of the microprocessor interface. not driven when cs =1 or rst =0. spi_cpha (spi_sel=1). when in spi mode, setting this bit to 1 inverts the phase of the clock signal on spick. see section 2.10 for detailed timing and functionality information. default setting is low. d7/ spi_cpol m9 l5 ioz data bit 7. bi-directional data bit 7 of the microprocessor interface. not driven when cs =1 or rst =0. spi_cpol (spi_sel=1). when in spi mode, setting this bit to 1 inverts the clock signal on spick. see section 2.10 for detailed timing and functionality information. default setting is low. cs j8 j3 i chip select. this pin must be taken low for read/write operations. when cs is high, the rd / d s and wr signals are ignored. rd / ds j9 ? i read data strobe (intel mode). the device drives the data bus with the contents of the addressed register while rd and cs are both low. data strobe (motorola mode). used to latch data through the microprocessor interface. ds must be low during read and write operations. wr /r w j10 ? i write (intel mode). the device captures the c ontents of the data bus on the rising edge of wr and writes them to the addressed register location. cs must be held low during write operations. read write (motorola mode). used to indicate read or write operation. r w must be set high for a register read cycle and low for a register write cycle. ale j7 ? i address latch enable. this signal is used to internally latch an address, allowing multiplexing of the parallel interface address and data lines. when ale is high, the values of the a[10:0] pins are used for read/write operations. on the falling edge of ale, the values of the a[10:0] pins are latched internally, and the latched value is used for read/write operations until the next rising edge of ale. ale should be tied high for non- multiplexed address systems. mode j12 ? i mode. selects rd / wr or ds strobe mode. 0 = read/write strobe mode 1 = data strobe mode int j11 g5 oz interrupt output. outputs a logic zero when an unmasked interrupt event is detected. int is de-asserted when all interrupts have been acknowledged and serviced. active low. inactive state is configured with the gl.cr2.intm bit. spi_sel j16 ? i parallel/spi interface select 0 = parallel interface 1 = spi interface selected
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 23 of 375 package pins name 256 144 type function gmii/mii/rmii port txd[0]/txd1[0], txd[1]/txd1[1], txd[2]/txd1[2], txd[3]/txd1[3], txd[4]/txd2[0], txd[5]/txd2[1], txd[6]/txd2[2], txd[7]/txd2[3] j13, k15, j15, h13, n15, p15, r15, t15 j8, j9, h8, h9, l8, k8, l9, k9 o transmit data 0 through 7(gmii mode). txd[0:7] is presented synchronously with the rising edge of tx_clk1. txd[0] is the least significant bit of the data. when tx _en1 is low the data on txd should be ignored. mac 1 transmit data 0 throug h 3(mii mode ? txd1[0:3]). four bits of data txd1[0:3] presented synchronously with the rising edge of tx_clk1. mac 1 transmit data 0 through 1(rmii mode ? txd1[0:1]). two bits of data txd1[0:1] presented synchronously with the rising edge of tx_clk1. mac 2 transmit data 0 thr ough 3(mii mode? txd2[0:3]). four bits of data txd2[0:3] presented synchronously with the rising edge of tx_clk2. note that txd2[0:3] is only available on devices with two ethernet ports. mac 2 transmit data 0 thr ough 1(rmii mode? txd2[0:1]). two bits of data txd2[0:1] presented synchronously with the rising edge of tx_clk2. note that txd2[0:1] is only available on devices with two ethernet ports. rxd[0]/rxd1[0], rxd[1]/rxd1[1], rxd[2]/rxd1[2], rxd[3]/rxd1[3], rxd[4]/rxd2[0], rxd[5]/rxd2[1], rxd[6]/rxd2[2], rxd[7]/rxd2[3] g14, f13, f14, h14, n16, m16, l15, k16 j10, j11, h10, h11, l10, l11, k10, k11 i mac 1 receive data 0 through 7(gmii mode). eight bits of received data, sampled synchronously with the rising edge of rx_clk. for every clock cycle, the phy transfers 8 bits to the device. rxd[0] is the least significant bit of the data. data is not considered valid when rx_dv is low. mac 1 receive data 0 through 3(mii mode ? rxd1[0:3]). four bits of received data, sampled synchronously with rx_clk1. accepted when rx_crs1 is asserted. mac 1 receive data 0 through 1(rmii mode ? rxd1[0:1]). two bits of received data, sampled synchronously with rx_clk1. accepted when rx_crs1 is asserted. mac 2 receive data 0 through 3(mii mode ? rxd2[0:3]): four bits of received data, sampled synchronously with rx_clk2. accepted when rx_crs2 is asserted. mac 2 receive data 0 through 1(rmii mode ? rxd2[0:1]). two bits of received data, sampled synchronously with rx_clk2. accepted when rx_crs2 is asserted. rx_clk1, rx_clk2 g16, n13 j12 io receive clock 1 (gmii). 125mhz clock. this clock is used to sample the rxd[7:0] data. receive clock 1 (mii). timing reference for rx_dv, rx_err and rxd[3:0], which are clocked on the rising edge. rx_clk frequency is 25mhz for 100mbps operation and 2.5mhz for 10mbps operation. in dte mode, this is a clock input provided by the phy. receive clock 2 (mii only). timing reference for rx_dv2, rx_err2 and rxd2[3:0], which are clocked on the rising edge. rx_clk2 frequency is 25mhz for 100mbps operation and 2.5mhz for 10mbps operation. in dte mode, this is a clock input provided by the phy. note that rx_clk2 is only available on devices with two ethernet ports. tx_clk1, tx_clk2 m15, t16 l12 io transmit clock 1 (mii). timing reference for tx_en1 and txd1[3:0]. the tx_clk1 frequency is 25mhz for 100mbps operation and 2.5mhz for 10mbps operation. in dte mode, this is a clock input provided by the phy. sourced from ref_clk input. transmit clock 2 (mii only). timing reference for tx_en2 and txd2[3:0]. the tx_clk2 frequency is 25mhz for 100mbps operation and 2.5mhz for 10mbps operation. in dte mode, this is a clock input provided by the phy. note that tx_clk2 is only ava ilable on devices with two ethernet ports. sourced from ref_clk input.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 24 of 375 package pins name 256 144 type function tx_en1, tx_en2 k14, p16 f8 o transmit enable 1(gmii). when this signal is asserted, the data on txd[7:0] is valid. transmit enable 1, 2 (mii/rmii). in m ii mode, this pin is asserted high when data txd[3:0] is being provided by the device. in rmii mode, this pin is asserted high when data txd[1: 0] is being provided by the device. the signal is deasserted prior to the first nibble of the next frame. this signal is synchronous with the rising edge tx_clk. it is asserted with the first bit of the preamble. note that tx_en2 is only available on devices with two ethernet ports. unused output pins should not be connected. rx_dv1, rx_dv2 g15, m11 f9 i receive data valid 1 (gmii). this signal is synchronous to the rx_clk1 and provides a valid signal for the rxd[7:0]. receive data valid 1, 2 (mii/rmii). this active-high signal indicates valid data from the phy. in mii mode the data rxd[3:0] is ignored if rx_dv is not asserted high. in rmii mode the data rxd[1:0] is ignored if rx_dv is not asserted high. note that rx_dv2 is only available on devices with two ethernet ports. rx_crs1, rx_crs2 e13, j14 g12 i receive carrier sense 1 (gmii). this signal is asserted (high) when data is valid from the phy. this signal is asserted by the phy when either transmit or receive medium is active. this signal is not synchronous to any of the clocks. receive carrier sense 1, 2 (mii). this signal is asserted by the phy when either transmit or receive medium is active. this signal is not synchronous to any of the clocks. note that rx_crs2 is only available on devices with two ethernet ports. rx_err1, rx_err2 h15, m12 g9 i receive error 1 (gmii). this signal indicates a receive error or a carrier extension in the gmii mode. receive error 1, 2 (mii). asserted by the mac phy for one or more rx_clk periods indicating that an error has occurred. active high indicates receive code group is invalid. if rx_crs is low, rx_err has no effect. this is synchronous with rx_clk. in dce mo de, this signal must be grounded. note that rx_err2 is only available on devices with two ethernet ports. tx_err1, tx_err2 l14, r16 g8 o transmit error 1(gmii). when this signal is asserted, the phy will respond by sending one or more code groups in error. transmit error 1, 2(gmii, mii). when this signal is asserted, the phy will respond by sending one or more code groups in error. note that tx_err2 is only available on devices with two ethernet ports. col1, col2 e14, l16 g10 i collision detect 1, 2 (mii). asserted by the ethernet phy to indicate that a collision is occurring. in dce mode this signal should be connected to ground. this signal is only valid in half duplex mode, and is ignored in full duplex mode. note that col2 is only available on devices with two ethernet ports. dcedtes p13 l7 i dce or dte selection (mii). setting this pin high places all ethernet ports in dce mode. setting this pin low places the ethernet ports in dte mode. in dce mode, the mii interface c an be directly connected to another mac. in dce mode, the transmit clock (tx_clk) and receive clock (rx_clk) are outputs. note that there is no software bit selection of dcedtes. note that dce operation is only valid for 10/100, mii mode. rmii_sel m14 k7 i rmii selection input. set this pin to 1 for rmii operation. in devices with 2 ethernet ports, both ports will oper ate in rmii mode. ref_clk must be 50mhz. set this pin to 0 for gmii or mii operation.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 25 of 375 package pins name 256 144 type function ref_clk t13 m8 i reference clock input. ref_clk must be 125mhz for gmii operation. ref_clk must be 25mhz for mii dce operation. ref_clk must be 50mhz for rmii operation. gtx_clk r14 m10 o gbe transmit clock output (gmii). 125mhz clock output available for gmii operation. this clock is sourced from the 125mhz ref_clk input. phy management bus mdc f15 h5 o management data clock. clocks mana gement data to and from the phy. the clock is derived from sysclki, with a maximum frequency is 1.67mhz. mdio g13 h4 io mii management data io. data path for control information between the device and the phy. pull to logic high externally through a 1.5 k resistor. the mdc and mdio pins are used to write or read up to 32 control and status registers in phy controllers. th is port can also be used to initiate auto-negotiation for the phy. sdram controller sdata[0] c16 a11 sdata[1] b16 b11 sdata[2] b15 d11 sdata[3] c15 c11 sdata[4] a14 a10 sdata[5] c12 b10 sdata[6] a13 d10 sdata[7] b13 c10 sdata[8] d9 c8 sdata[9] c9 d8 sdata[10] d12 b8 sdata[11] c10 e9 sdata[12] b10 c9 sdata[13] b11 d9 sdata[14] c11 b9 sdata[15] b12 a9 ioz sdram data bus bits 0 through 15. the 16 pins of the sdram data bus are inputs for read operations and outputs for write operations. at all other times, these pins are high impedance. sda[0] c3 a3 sda[1] c2 d2 sda[2] b2 b2 sda[3] a2 d1 sda[4] d3 c1 sda[5] d4 e1 sda[6] b5 c2 sda[7] c5 e2 sda[8] d5 b3 sda[9] b6 a4 sda[10] a3 c3 sda[11] c6 b4 sda[12] a5 d3 o sdram address bus 0 through 12. the 13 pins of the sdram address bus output the row address first, followed by the column address. the row address is determined by sda[0] to sd a[12] at the rising edge of clock. column address is determined by sda[0]-sda[9] and sda[11] at the rising edge of the clock. sda[10] is used as an auto-precharge signal. sba[0], sba[1] b4, b3 d4, c4 i sdram bank select. these 2 bits select 1 of 4 banks for the read/write/precharge operations. sdcs a4 a5 o sdram chip select. all commands are masked when sdcs is registered high. sdcs provides for external bank selection on systems with multiple banks. sdcs is considered part of the command code.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 26 of 375 package pins name 256 144 type function sras a6 b5 o sdram row address strobe. active-low output, used to latch the row address on rising edge of sd_clk. it is used with commands for bank activate, precharge, and mode register write. scas b7 d5 o sdram column address strobe. active low output, used to latch the column address on the rising edge of sd_clk. it is used with commands for bank activate, precharge, and mode register write. swe a7 c5 o sdram write enable. this active low output enables write operation and auto precharge. sd_udm d7 e7 o sdram upper data mask. sd_udm is an active high output mask signal for write data. sd_udm is updated on both edges of sd_udqs. sd_udm corresponds to data on sdata15-sdata8. sd_ldm d13 e6 o sdram lower data mask. sd_ldm is an active high output mask signal for write data. sd_ldm is updated on both edges of sd_ldqs. sd_ldm corresponds to data on sdata7-sdata0. sd_ldqs c13 e8 ioz lower data strobe. output with write data, input with read data. sd_ldqs corresponds to data on sdata7-sdata0. sd_udqs d8 d7 ioz upper data strobe. output with write data, input with read data. sd_udqs corresponds to data on sdata15-sdata8. sd_clk a8 a8 o sdram clock. sd_clk and sd_clk are differential clock outputs. all address and control input signals are sampled on the crossing of the positive edge of sd_clk and negativ e edge of sd_clk. output (write) data is referenced to the crossings of sd_clk and sd_clk (both directions of crossing). sd_clk a9 a7 o sdram clock (inverted). sd_clk and sd_clk are differential clock outputs. all address and control input signals are sampled on the crossing of the positive edge of sd_clk and negative edge of sd_clk. output (write) data is referenced to the crossings of sd_clk and sd_clk (both directions of crossing). sd_clken c4 e5 o sdram clock enable. active high. sd_clken must be active throughout ddr sdram read and write accesses. serial interface io pins tdata1 t6 l3 tdata2 t7 ? tdata3 p6 ? tdata4 n9 ? tdata5 m5 ? tdata6 n6 ? tdata7 n7 ? tdata8 r9 ? tdata9 n10 ? tdata10 r11 ? tdata11 n11 ? tdata12 r12 ? tdata13 p14 ? tdata14 p12 ? tdata15 n12 ? tdata16 p11 ? o transmit serial data output. output on the rising edge of tclk. the maximum data rate is 52mbps. not all serial port signals are available on all products in the device family. unused output pins should not be connected. ds33x41/x42/w41/w11: tdat a5 ? tdata16 not used. ds33x81/x82: tdata9 ? tdata16 not used. tclk1/tmclk1 r5 m3 tclk2 p5 ? tclk3 r8 ? tclk4 p9 ? i serial interface transmit clock input (tclk[1:8]). the clock reference for tdata, which is output on the rising edge of the clock. tclk supports gapped clocking, up to a maximum frequency of 52mhz. note that tclk1 is also tmclk1, tclk5 is also tmclk2. tmclk3 and tmclk4 are stand-alone pins.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 27 of 375 package pins name 256 144 type function tclk5/tmclk2 m7 ? tclk6 p10 ? tclk7 t10 ? tclk8 r10 ? tmclk3 t11 ? tmclk4 m10 ? transmit master clock (tmclk[1:4]). input clock that tdata is referenced to. this clock may be gapped. maximum clock speed is 52mhz. this clock can be inverted. not all serial port signals are available on all products in the device family. unused input pins should be tied to vss. ds33x41/x42/w41/w11: tc lk5 ? tclk8 not used. tsync1/ tmsync1 r6 m4 tsync2 t8 ? tsync3 m6 ? tsync4 p7 ? tsync5/ tmsync2 r7 ? tsync6 p8 ? tsync7 n8 ? tsync8 t9 ? tmsync3 t12 ? tmsync4 n14 ? i transmit synchronization input (tsync[1:8]). input that indicates frame boundaries on tdata, referenced to tclk. this signal may be a frame or multiframe sync. it must be a multiframe sync for vcat applications. data is octet aligned to this signal. note that tsync1 is also tm sync1, tsync5 is also tmsync2. tmsync3 and tmsync4 are stand-alone pins. transmit master sync (tmsync[1:4]). this input indicates frame boundaries on tdata if selected via li.tcr.td_sel, referenced to tmclk1. not all serial port signals are available on all products in the device family. unused input pins should be tied to vss. ds33x41/x42/w41/w11: tsync5 ? ttsync8 not used. rdata1 d1 j2 rdata2 g8 ? rdata3 g4 ? rdata4 h2 ? rdata5 f3 ? rdata6 f2 ? rdata7 k1 ? rdata8 l1 ? rdata9 k2 ? rdata10 k3 ? rdata11 n1 ? rdata12 l4 ? rdata13 p2 ? rdata14 r1 ? rdata15 n3 ? rdata16 n4 ? i receive serial data input (rdata[1:16]). receive serial data from a t1/e1/t3/e3/xdsl framer. data input on the rising edge of rclk. not all serial port signals are available on all products in the device family. unused input pins should be tied to vss. ds33x41/x42/w41/w11: rda ta5 ? rdata16 not used. ds33x81/x82: rdata9 ? rdata16 not used.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 28 of 375 package pins name 256 144 type function rclk1 e1 g1 rclk2 g7 ? rclk3 g1 ? rclk4 h4 ? rclk5 f4 ? rclk6 j1 ? rclk7 j5 ? rclk8 j4 ? rclk9 j3 ? rclk10 j2 ? rclk11 m2 ? rclk12 n2 ? rclk13 l5 ? rclk14 t1 ? rclk15 t4 ? rclk16 r3 ? i serial interface receive clock input (rclk[1:16]). reference clock for receive serial data on rdata. gapped clocking is supported, up to the maximum rclk frequency of 52mhz. not all serial port signals are available on all products in the device family. unused input pins should be tied to vss. ds33x41/x42/w41/w11: rcl k5 ? rclk16 not used. ds33x81/x82: rclk9 ? rclk16 not used. rsync1 f1 j1 rsync2 h7 ? rsync3 g2 ? rsync4 h1 ? rsync5 g3 ? rsync6 h3 ? rsync7 n5 ? rsync8 l2 ? rsync9 k4 ? rsync10 m1 ? rsync11 l3 ? rsync12 p1 ? rsync13 m4 ? rsync14 r2 ? rsync15 p3 ? rsync16 t3 ? i receive frame/multiframe sync hronization input (rsync[1:16]). receive sync that indicates frame boundaries or multiframe boundaries for t1/e1/t3/e3 signals present on rda ta. it must be a multiframe sync for vcat applications. not all serial port signals are available on all products in the device family. unused input pins should be tied to vss. ds33x41/x42/w41/w11: rsy nc5 ? rsync16 not used. ds33x81/x82: rsync9 ? rsync16 not used. voice interface io pins - ds33w41 and ds33w11 only tvdata m5 ? i transmit voice data input. input voice data stream containing multiple ds0s. referenced to tvclk. disabled when tvden is high. this signal is only available on the ds33w41 and ds33w11. tvclk m7 ? i transmit voice clock input. input clock that times tvdata. may be gapped. maximum clock speed 52mhz. this signal is only available on the ds33w41 and ds33w11. tvsync r7 ? i transmit voice synchronization input. input signal that indicates frame boundaries on voice data stream (tvdata), sampled by tvclk, frequency of 8 khz. this signal is only available on the ds33w41 and ds33w11. tvden n6 ? i transmit voice data enable. may be used in place of a gapped tvclk. if low, tvdata is valid. if a gapped tvclk is used and this signal is not used, tie this input low. this signa l is only available on the ds33w41 and ds33w11. rvdata f2 ? o receive voice data output. outputs voice data stream from internal fifo using rvclk. maximum ds0s is dependent on wan data rate (t1 max is 24, e1 is 31). this is a tri-state output, high impedance when rvden is high. this signal is only available on the ds33w41 and ds33w11. rvclk f3 ? i receive voice clock input. receive clock that times rvdata signal. may be gapped. maximum clock speed 52mhz. this signal is only available on the ds33w41 and ds33w11.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 29 of 375 package pins name 256 144 type function rvsync f4 ? i receive voice synchronization input. receive sync that indicates frame boundaries present on rvdata ? referenced to rvclk, frequency of 8 khz. this signal is only available on the ds33w41 and ds33w11. rvden g3 ? i receive voice data enable: may be used in place of a gapped rvclk. if low, rvdata is valid. if gapped rvclk is used and this signal is not used, tie this input low. this signa l is only available on the ds33w41 and ds33w11. hardware and status pins hiz h16 f10 i high-impedance test enable (active low). this signal puts all digital output and bi-directional pins in the high impedance state when it is low and jtrst is low. for normal operation tie high. this is an asynchronous input. rst e8 f2 i reset (active low). an active low signal on this pin resets the internal registers and logic. while this pin is held low, the microprocessor interface is kept in a high-impedance state. this pin should remain low until power is stable and then set high for normal operation. system clocks sysclki e16 e12 i system clock in: 125mhz, 100ppm system clock input. jtag interface jtrst b1 g4 ipu jtag reset (active low). jtrst is used to asynchronously reset the test access port controller. after power-up, a rising edge on jtrst will reset the test port and cause the devic e i/o to enter the jtag device id mode. pulling jtrst low restores normal device operation. jtrst is pulled high internally via a 10k resistor operation. if boundary scan is not used, this pin should be held low. jtclk a1 g3 ipu jtag clock. this signal is used to shift data into jtdi on the rising edge and out of jtdo on the falling edge. jtdo e2 h2 oz jtag data out. test instructions and data are clocked out of this pin on the falling edge of jtclk. if not used, this pin should be left unconnected. jtdi d2 h3 ipu jtag data in. test instructions and data are clocked into this pin on the rising edge of jtclk. this pin has a 10k pullup resistor. jtms c1 g2 ipu jtag mode select. this pin is sampled on the rising edge of jtclk and is used to place the test access port into the various defined ieee 1149.1 states. this pin has a 10k pullup resistor. power supplies vdd3.3 e10, e12, e9, f7, g5, k5, m8, p4, t14 f3, f11, h1, h6, h7, k12, m2, m7 i connect to 3.3v power supply vdd1.8 d11, e3, e4, f12, g12, h11, h12, m3, r13 f1, g6, g7, h12, l1, m5, m11 i connect to 1.8v power supply
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 30 of 375 package pins name 256 144 type function vss a10, c7, f6, f8, f9, f10, f11, f16, g6, g9, h5, h9, h10, m13, r4, t5 f6, f7, f12, g11, j6, j7, k1, k2, k6, l6, m1, m6, m9, m12 i ground connection for 3.3v and 1.8v supplies. connect to the common supply ground. avdd f5 d12 i analog pll power. connect to a 1.8v power supply. avss e11 c12 i analog pll ground vdd2.5 b8, e5, e7 b1, c6 i sdram digital power. connect to a 2.5v power supply. vddq a11, a12, a15, a16, c14, d10, d14 a2, b12, c7, e4, e10 i sdram digital dq power. connect to a 2.5v ( 0.2v) . vssq b14, c8, d6, d15, d16, e15, e6 a1, a6, a12, b6, b7, e3, e11 i sdram digital ground. vref b9 d6 i sdram sstl_2 reference voltage for sdram. must equal one-half vddq. can be derived from a resistor-divider. dnc h6, h8, j6, t2 f4, f5, k3, l2 ? do not connect. do not connect these pins. notes: i = input oz = output, with tri-state o = output io = bi-directional pin ipu = input, with pullup ioz = bi-directional pin, with tri-state
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 31 of 375 figure 7-1. 256-ball, 17mm x 17mm csbga pinout (DS33X162/x161/ x82/x81/x42/x41) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a jtclk sda[3] sda[10] sdcs sda[12] sras swe sd_clk sd_clk vss vddq vddq sdata[6] sdata[4] vddq vddq b jtrst sda[2] sba[1] sba[0] sda[6] sda[9] scas vdd2.5 vref sd ata[12] sdata[13] sdata[15] sdata[7] vssq sdata[2] sdata[1] c jtms sda[1] sda[0] sd_clke n sda[7] sda[11] vss vssq sdata[9] sdata[11] sdata[14] sdata[5] sd_ldqs vddq sdata[3] sdata[0] d rdata1 jtdi sda[4] sda[5] sda[8] vssq sd_udm sd_udqs sdata[8] vddq vdd1.8 sdata[10] sd_ldm vddq vssq vssq e rclk1 jtdo vdd1.8 vdd1.8 vdd2.5 vssq vdd2.5 rst vdd3.3 vdd3.3 avss vdd3.3 rx_crs1 col1 vssq sysclki f rsync1 rdata6 rdata5 rclk5 avdd vss vdd3.3 vss vss vss vss vdd1.8 rxd[1] / rxd1[1] rxd[2] / rxd1[2] mdc vss g rclk3 rsync3 rsync5 rdata3 vdd3.3 vss rclk2 rdata2 vss a8 a10 vdd1.8 mdio rxd[0] / rxd1[0] rx_dv1 rx_clk1 h rsync4 rdata4 rsync6 rclk4 vss dnc rsync2 dnc vss vss vdd1.8 vdd1.8 txd[3] / txd1[3] rxd[3] / rxd1[3] rx_err1 hiz j rclk6 rclk10 rclk9 rclk8 rclk7 dnc ale cs rd / ds wr / r w int mode txd[0] / txd1[0] rx_crs2 txd[2] / txd1[2] spi_sel k rdata7 rdata9 rdata10 rsync9 vdd3.3 d0 / spi_miso d2 / spi_clk d4 d6 / spi_cpha a0 a2 a6 a4 tx_en1 txd[1] / txd1[1] rxd[7] / rxd2[3] l rdata8 rsync8 rsync11 rdata12 rclk13 d1 / spi_mosi d3 d5 /spi_ swap a1 a3 a5 a7 a9 tx_err1 rxd[6] / rxd2[2] col2 m rsync10 rclk11 vdd1.8 rsync13 tdata5 tsync3 tclk5 vdd3.3 d7 / spi_cpol tmclk4 rx_dv2 rx_err2 vss rmii_sel tx_clk1 rxd[5] / rxd2[1] n rdata11 rclk12 rdata15 rdata16 rsync7 tdata6 tdata7 tsync7 tdata4 tdata9 tdata11 tdata15 rx_clk2 tmsync4 txd[4] / txd2[0] rxd[4] / rxd2[0] p rsync12 rdata13 rsync15 vdd3.3 tclk2 tdata3 tsync4 tsync6 tclk4 tclk6 tdata16 tdata14 dcedtes tdata13 txd[5] / txd2[1] tx_en2 r rdata14 rsync14 rclk16 vss tclk1 tsync1 tsync5 tclk3 tdata8 tclk8 tdata10 tdata12 vdd1.8 gtx_clk txd[6] / txd2[2] tx_err2 t rclk14 dnc rsync16 rclk15 vss tdata1 tdata2 tsync2 tsync8 tclk7 tmclk3 tmsync3 ref_clk vdd3.3 txd[7] / txd2[3] tx_clk2 note: shaded pins do not apply to all devices in the product family . see the pin listing for specific pin availability. in the high port count devices, the shaded input pins do not have pullup/pul-d own resistors. consideration must be taken during board design to bias the inputs appropriately, and to float output pi ns (tdata5-tdata16, tx_en2, tx_err2) if lower port count designs are to be potentially stuffed with higher port count devices.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 32 of 375 figure 7-2. 256-ball, 17mm x 17mm csbga pinout (ds33w41/ds33w11) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a jtclk sda[3] sda[10] sdcs sda[12] sras swe sd_clk sd_clk vss vddq vddq sdata[6] sdata[4] vddq vddq b jtrst sda[2] sba[1] sba[0] sda[6] sda[9] scas vdd2.5 vref sd ata[12] sdata[13] sdata[15] sdata[7] vssq sdata[2] sdata[1] c jtms sda[1] sda[0] sd_clke n sda[7] sda[11] vss vssq sdata[9] sdata[11] sdata[14] sdata[5] sd_ldqs vddq sdata[3] sdata[0] d rdata1 jtdi sda[4] sda[5] sda[8] vssq sd_udm sd_udqs sdata[8] vddq vdd1.8 sdata[10] sd_ldm vddq vssq vssq e rclk1 jtdo vdd1.8 vdd1.8 vdd2.5 vssq vdd2.5 rst vdd3.3 vdd3.3 avss vdd3.3 rx_crs1 col1 vssq sysclki f rsync1 rvdata rvclk rvsync avdd vss vdd3.3 vss vss vss vss vdd1.8 rxd[1] / rxd1[1] rxd[2] / rxd1[2] mdc vss g rclk3 rsync3 rvden rdata3 vdd3.3 vss rclk2 rdata2 vss a8 a10 vdd1.8 mdio rxd[0] / rxd1[0] rx_dv1 rx_clk1 h rsync4 rdata4 rclk4 vss dnc rsync2 dnc vss vss vdd1.8 vdd1.8 txd[3] / txd1[3] rxd[3] / rxd1[3] rx_err1 hiz j dnc ale cs rd / ds wr / r w int mode txd[0] / txd1[0] txd[2] / txd1[2] spi_sel k vdd3.3 d0 / spi_miso d2 / spi_clk d4 d6 / spi_cpha a0 a2 a6 a4 tx_en1 txd[1] / txd1[1] rxd[7] / rxd2[3] l d1 / spi_mosi d3 d5 /spi_ swap a1 a3 a5 a7 a9 tx_err1 rxd[6] / rxd2[2] m vdd1.8 tvdata tsync3 tvclk vdd3.3 d7 / spi_cpol vss rmii_sel tx_clk1 rxd[5] / rxd2[1] n tvden tdata4 txd[4] / txd2[0] rxd[4] / rxd2[0] p vdd3.3 tclk2 tdata3 tsync4 tclk4 dcedtes txd[5] / txd2[1] r vss tclk1 tsync1 tvsync tclk3 vdd1.8 gtx_clk txd[6] / txd2[2] t dnc rclk15 vss tdata1 tdata2 tsync2 ref_clk vdd3.3 txd[7] / txd2[3] note 1: shaded pins do not apply to all devices in the product family. see the pin listing for specific pin availability. note 2: the tvden pin is an input on the ds33w41/ds33w11, and is an output pin on other devices in the product family.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 33 of 375 figure 7-3. 144-ball, 10mm x 10mm, csbga pinout (ds33x11) 1 2 3 4 5 6 7 8 9 10 11 12 a vss vddq sda[0] sda[9] sdcs vss sd_clk sd_clk sdata[15] sdata[4] sdata[0] vss b vdd2.5 sda[2] sda[8] sda[11] sras vss vss sdata[10] sdata[14] sdata[5] sdata[1] vddq c sda[4] sda[6] sda[10] sba[1] swe vdd2.5 vddq sdata[8] sdata[12] sdata[7] sdata[3] avss d sda[3] sda[1] sda[12] sba[0] scas vref sd_udq s sdata[9] sdata[13] sdata[6] sdata[2] avdd e sda[5] sda[7] vss vddq sd_clken sd_ldm sd_udm sd_ldqs sdata[11] vddq vss sysclki f vdd1.8 rst vdd3.3 dnc dnc vss vss tx_en1 rx_dv1 hiz vdd3.3 vss g rclk1 jtms jtclk jtrst int vdd1.8 vdd1.8 tx_err1 rx_err1 col1 vss rx_crs1 h vdd3.3 jtdo jtdi mdio mdc vdd3.3 vdd3.3 txd[2] txd[3] rxd[2] rxd[3] vdd1.8 j rsync1 rdata1 cs spi_miso spi_swap vss vss txd[0] txd[1] rxd[0] rxd[1] rx_clk1 k vss vss dnc spi_mosi spi_cpha vss rmii_sel txd[5] txd[7] rxd[6] rxd[7] vdd3.3 l vdd1.8 dnc tdata1 spi_clk spi_cpol vss dcedtes txd[4] txd[6] rxd[4] rxd[5] tx_clk1 m vss vdd3.3 tclk1 tsync1 vdd1.8 vss vdd3.3 ref_clk vss gtx_clk vdd1.8 vss note that the parallel bus is not available in the 144-pin ds 33x11, and the spi slave port must be used for processor control.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 34 of 375 8. functional description the DS33X162 family of devices provide interconnecti on and mapping functionality between ethernet systems and wan time-division multiplexed (tdm) systems such as t1/e1/j1, hdsl, t3/e3, and sonet/sdh. the device is composed of up to two 10/100/1000 ethernet macs, up to 16 serial ports, a arbiter, gfp/hdlc/chdlc/x.86 (laps) mappers, a ddr sdram in terface, and control ports. ethernet traffic is encapsulated with gfp-f, hdlc, chdlc, or x.86 (laps) to be transmitted over the wan serial interfaces. the wan serial interfaces also receive encapsulated ethernet frames and transmit the extracted frames over the ethernet ports. the lan interface consists of ethernet macs using on e of two physical layer protocols. the interface can be configured with up to two 10/100mbps mii/rmii ports or a single gbe gmii po rt. the mii/rmii and gmii interfaces allow connection to commercially available ethernet phy and mac devices. the wan physical interface supports 8 serial data st reams up to 52mbps each. the DS33X162 and ds33x161 support an additional 8 serial data streams with data rate s up to 2.5mbps each. the wan serial interfaces receive encapsulated ethernet frames and transmit the extracted fr ames over the ethernet ports. the wan serial ports can operate with a gapped clock, and can be connected to a framer , electrical liu, optical transceiver, or t/e-carrier transceiver for transmission to the wan. the serial interfaces can be seamlessly connected to the maxim t1/e1/j1 framers, line interface units (lius), and single- chip transceivers (scts). the wan interfaces can also be seamlessly connected to the maxim t3/e3/sts-1 fram ers, lius, and scts to provide t3, e3, and sts1 connectivity. ethernet frames are queued and stored in an external 32-b it ddr sdram. the ddr sd ram controller enables connection to a 256mb sdram without external glue logic, at clock frequencies up to 125mhz. the sdram is used for the lan data, wan data, frame extraction, and frame insertion queues. the user can program a ?near full threshold? (watermark) for the la n and wan queues that can be used to in itiate automatic flow control. the device also provides the capability for x 43 +1 payload and barker sequence scrambling. microprocessor control can be accomplished through a 8-bit micro controller port or spi bus. the device has a 125mhz ddr sdram controller and interfaces to a 32-bit wide 256mb ddr sdram via a 16-bit data bus. the ddr sdram is used to buffer data from the ethernet and wan ports for transport. the power supplies consist of a 1.8v core supply , a 2.5v ddr sdram supply, and 3.3v i/o supply.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 35 of 375 8.1 parallel processor interface configuration and control can be accomplished through the 8- bit parallel microprocessor port. the device?s 16-bit registers are accessed as sequential byte addresses. the 8-bit parallel data bus can be configured for intel or motorola modes of operation. the 8-bit parallel data bus ca n be configured for intel or motorola modes of operation with the mode pin. when mode = 0, bus timing is in intel mode, as shown in figure 12-13 and figure 12-14. when mode = 1, bus timing is in motorola mode, as shown in figure 12-15 and figure 12-16. the address space is mapped through the use of 11 address lines, a0-a10. an address latch enable [ale] pin is provided to allow for multiplexing of the data and address signals. note that th e parallel bus is not available in the 144 pin ds33x11, and the spi slave port must be used for processor control. the chip select ( cs ) pin must be brought to a logic low level to gain read and write access to the microprocessor port. with intel timing selected, the read ( rd ) and write ( wr ) pins are used to indicate read and write operations and latch data through the interface. with mo torola timing selected, the read-write ( r w ) pin is used to indicate read and write operations while the data strobe ( ds ) pin is used to latch data through the interface. the interrupt output pin ( int ) is an open-drain output that will assert a logic-low level upon a number of software maskable interrupt conditions. the inactive stat e of this pin can be configured with the gl.cr2.intm bit. this pin is normally connected to the microprocessor inte rrupt input. the register map is shown in table 10-1 on page 105. 8.1.1 read-write/data strobe modes the processor interface can operate in either read-wri te strobe mode or data strobe mode. when mode = 0 the read-write strobe mode is enabled and a negative pulse on rd performs a read cycle, and a negative pulse on wr performs a write cycle. when mode pin = 1, the data strobe mode is enabled and a negative pulse on ds when r w is high performs a read cycle, and a negative pulse on ds when r w is low performs a write cycle. the read- write strobe mode is commonly called the ?intel? mode, and the data strobe mode is commonly called the ?motorola? mode. 8.1.2 clear on read the latched status registers will clear on a read access. it is important to note that in a multi-task software environment, the user should handle all status conditions of each register at the same time to avoid inadvertently clearing status conditions. the latched status register bits are carefully designed so that an event occurrence cannot collide with a user read access. 8.1.3 interrupt and pin modes the interrupt ( int ) pin is configurable to drive high or float when not active. the gl.cr2.intm bit controls the pin configuration, when it is set to 1, the int pin will drive high when inactive. after reset, the int pin is in high impedance mode until an interrupt source is acti ve and enabled to drive the interrupt pin. 8.1.4 multiplexed bus operation an address latch enable [ale] pin is provided to allo w for multiplexing of the data and address signals. for multiplexed operation, each of the eight data lines (d0-d7) must be externally connected to each of the lower eight address lines (a0-a7). the remaining address lines (a8-a1 0) are connected as normal. address inputs are latched upon the falling edge of the ale signal. ale must remain low until the read or write operation is complete.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 36 of 375 8.2 spi serial processor interface the spi interface is a four-signal serial interface that allows configuration and monitoring of the device with a minimal number of electrical connections. the spi inte rface uses full-duplex spi slave operation. the maximum clock frequency of the spi interface is 10mhz. each access (read or write) takes approximately 2.4 s. with two address/control bytes required for each data byte, t he maximum data throughput rate is approximately 3.3 megabits per second. see the section 11.1 for functional timing diagrams, and section 12 for ac parametric timing. note that the parallel bus is not available in the 144-pin ds33x11, and the spi slave port must be used for processor control. the spi bus is implemented using four signals: clock (spi _clk), master-out slave-in data (spi_mosi), master-in slave-out data (spi_miso), and chip select ( cs ). spi_clk polarity and phase can be set by the spi_cpol and spi_cpha pins. the order of the address and data bits in t he serial stream is selectable using the spi_swap pin. the read/write (r/w) bit is always the first bit and the burst (b) bit is always last bit of the address/control bytes and their location is not affected by the spi_swap pin setting. note that spi ?burst mode? is not applicable for oam frame insertion or extraction, due to the indirect access of the extract and insert queues. the interface overhead associat ed with frame insertion and extraction is 5 register accesses per frame. the spi protocol defines four combinations of sck phase and polarity with respect to the data controlled by cpol (clock polarity) and cpha (clock phase): spi_cpol spi_cpha transfer 0 0 spi_clk rising-edge transfer. spi_clk transitions in middle of bit timing. 1 0 spi_clk falling-edge transfer. spi_clk transitions in middle of bit timing. 0 1 spi_clk falling-edge transfer. spi_clk transitions at beginning of bit timing. 1 1 spi_clk rising-edge transfer. spi_clk transitions at beginning of bit timing.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 37 of 375 8.3 clock structure the clock sources and functions are as follows: ? serial transmit data (tclkn) and serial receive data (rclkn) clock inputs are used to transfer data from the serial interface. these clocks can be continuous or gapped. ? the serial transmit clock for ports 9-12 is a shared cl ock (tmclk3). the serial transmit sync for ports 9- 12 is also shared (tmsync3). ? the serial transmit clock for ports 13-16 is a shared clock (tmclk4). the serial transmit sync for ports 13-16 is also shared (tmsync4). ? system clock (sysclki) input. used for internal operation. this clo ck input cannot be a gapped clock. a clock supply with +/- 100 ppm frequency accuracy is sugge sted. a buffered version of this clock is provided on the sd_clk pin for the operation of the sdram. ? the transmit and receive clocks fo r the mii/rmii interface (tx_clk and rx_clk). in dte mode, these are input pins and accept clocks provided by an ethernet phy. ? a management data clock (mdc) out put is derived from sysc lki and is used for information transfer between the internal ethernet mac and external phy. the mdc clock frequency is 1.67mhz. the device expects gapped clocks for t3/e3/t1/e1 dat a streams, minimally gapped for line overhead periods the following table provides the different cl ocking options for the ethernet interface. table 8-1. clocking options for the ethernet interface ethernet interface mode mii mii rmii gmii speed 100mbps 10mbps 10/100 mbps 1000 mbps tx_clkn frequency 25mhz 2.5mhz n/a n/a i/o rx_clkn frequency 25mhz 2.5mhz n/a 125mhz i/o ref_clk frequency 25mhz 25mhz 50mhz 125mhz input gtx_clk n/a n/a n/a 125mhz output mdc output clock frequency 1.67mhz 1.67mhz 1.67mhz 1.67mhz output rmii_sel input pin 0 0 1 0 input gl.cr1.p1spd / gl.cr1.p2spd 1 0 0=10mbps 1=100mbps n/a register su.maccr.gmiimiis 1 1 1 0 register * clock sources should be accurate to 100ppm.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 38 of 375 figure 8-1. clocking diagram (mii mode) rx_clk tx_clk mdc tclk1 rclk1 ethernet mac1 p port ddr sdram port sd_cl k sd_cl k arbiter/ buffer manager cir/cbs controller gfp/x.86/ hdlc/chdlc transmit serial port 1 jtag clad (mii mode) rx_clk tx_clk mdc ethernet mac2 (x162/82/42) sysclki ethernet brdige/filter spi qos vcat/lcas add/drop oam frames ethernet brdige/filter gfp/x.86/ hdlc/chdlc vcat/lcas transmit serial port 2 transmit serial port 16 receive serial port 1 receive serial port 2 receive serial port 16 tvcl k rvcl k voice port ( w41/w11 ) tclk2 tmclk4 rclk2 rclk16 spi_clk
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 39 of 375 8.3.1 serial interface clock modes serial interface timing is determined by the line clocks. both the transmit and receive clocks (tclk and rclk) are inputs, and can be gapped. 8.3.2 ethernet interface clock modes the ethernet interfaces can be configured for mii, rmii, or gmii operation with the gl.cr1.p1spd , gl.cr1.p2spd, su.maccr.gmiimiis bits and the rmii_sel input pin. see table 8-1 for details of the clock requirements for the various ethernet interface configurations. 8.4 resets and low-power modes the external rst pin and the reset bit gl.cr2.rst generate global reset signals. a global reset signal resets the status and control registers on the chip (except the gl.cr2.rst bit) to their default values and resets all the other flops to their reset values. the processor bus output signals are also placed in high-impedance mode when the rst pin is active (low). the global reset bit ( gl.cr2.rst ) stays set after a one is writt en to it, but is reset to zero when the external rst pin is active or when a zero is written to it. the system clock must be active for the device to properly execute the reset. allow 5 milliseconds after initia ting a reset condition for the reset operation to complete. the DS33X162 family of devices contain up to 54 individual software reset bits, depending on the port count of the device. these functions of the various reset bits are outlined in the table below. table 8-2. software reset functions bit location function gl.cr2.rst global device reset. su.bfc.bftr resets each of the 4096 bridge filter table entries. su.lp1c.lp1fr lan port fifo reset su.lp2c.lp2fr lan port fifo reset ar.lq1sa ? ar.lq16sa.lq n pr lan queue pointer reset ar.wq1sa ? ar.wq16sa.wq n pr wan queue pointer reset ar.liqsa.liqpr lan insert queue pointer reset ar.leqsa.leqpr lan extract queue pointer reset ar.wiqsa.wiqpr wan insert queue pointer reset ar.weqsa.weqpr wan extract queue pointer reset ar.mqc.asqpr lan queue, wan queue, lan insert queue, lan extract queue, wan insert queue, and wan extract queue reset. pp.dfscr.dsmr (1-4) decapsulator reset pp.dfscr.depre (1-4) pointer reset enable vcat.rcr4.rfrst (1-16) vcat receive fifo reset/power-down. li.tvpcr.tvfrst transmit voice fifo reset/power-down. li.rcr1.rfrst (1-16) receive fifo reset/power-down. li.rvpcr.rvrst receive voice fifo reset/power-down.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 40 of 375 there are several features included to reduce power consumption. the reset bits of the li.rcr1.rfrst, li.rvpcr.rvrst, li.tvpcr.tvfrst, and vcat.rcr4.rfrst registers also place the associated circuitry in a low-power mode. additionally, the rst pin may be held low indefinitely to keep the entire device in a low-power mode. note that exiting the low- power condition requires re-ini tialization and configuration. table 8-3. block enable functions block enables su.lp1c.lp1e lan port 1 enable su.lp2c.lp2e lan port 2 enable vcat.tcr1.tvblken transmit vcat enable vcat.rcr1.rvblken receive vcat enable (global) vcat.rcr1.rven1-rven4 receive vcat enable (per wan group) li.tvpcr.tpe transmit voice port enable li.rvpcr.rpe receive voice port enable su.bfc.bfe bridge filter enable
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 41 of 375 8.5 initialization and configuration example device initialization sequence: step 1: reset the device step 2: configure serial ports, tx vcat, rx vcat, encapsulator, decapsulator step 3: enable transmit serial, transmit vcat, encapsulator, receive lan step 4: enable transmit and receive mac1 ( su.maccr.te, su.maccr.re ) step 5: enable transmit and receive mac2 ( su.maccr.te, su.maccr.re ) step 6: enable receive vcat, decapsulator, transmit lan step 7: enable interrupts 8.6 global resources the set of global registers begin at address location 000h. the global registers include global resets, global interrupt status, interrupt masking, clock configuration, and the device id register s. see the global register definitions in table 10-2. 8.7 per-port resources the device contains a common set of global registers. the se rial (line) interfaces each have a set of registers for configuration and control, denoted in this document with t he ?li.? prefix. the ethernet (subscriber) interfaces each have a set of registers for configur ation and control, denoted in this document with the ?su.? prefix. 8.8 device interrupts figure 8-2 diagrams the flow of interrupt conditions from t heir source status bits thr ough the multiple levels of information registers and mask bits to the interrupt pin. when an interrupt occurs, the host can read the global interrupt status register gl.isr to initially determine the source of the in terrupt. the host can then read the higher- level status registers to further identify the source of the interr upt(s). all global status bits ( gl.isr ) and intermediate status bits ( ar.bmis , vcat.risr ) are real-time bits that will clea r once all appropriate interrupts have been serviced and cleared. the inte rrupts from any source ca n be blocked at a global level by the writing a zero in appropriate location in the global interrupt enable register gl.ier . some portions of the device use interrupt mask registers. placing a ?1? in the associated bit loca tion associated with an interrupt condition prevents that condition from causing a device interrupt. some portions of the device use interrupt enable registers. placing a ?1? in the associated bit location associated with an interrupt condition allows that condition to cause a device interrupt. latched status bits that have been enabled or are un-masked are allowed to pass their interrupt conditions to the global interrupt status registers. t he interrupt enable registers allow individual latched status conditions to generate an interrupt, but when set to zero, they do not pr event the latched status bits from being set. therefore, when servicing interrupts, the user s hould and the latched status with the as sociated interrupt enable register in order to exclude bits for which the user wished to prevent interrupt service. the user should nand the latched status bits with the associated interrupt mask register. latched status registers clear once read as described in section 8.1.2. this architecture allows t he application host to periodically po ll the latched status bits for non- interrupt conditions, while using only one set of registers. note that the inactive state of the in terrupt output pin is configurable. the gl.cr2.intm bit controls the inactive state of the interrupt pin, allowing se lection of high-impedance or active driver . the interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. the latched status bits for the interrupting entity must be read to clear the interrupt. note that reading one latched status bit will reset all bits in that register. during a reset condition, interrupts cannot be generated.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 42 of 375 figure 8-2. device interrupt information flow diagram drawing legend: status / interrupt source register / bit name interrupt enable/ mask registers register / bit name interrupt pin 0 rxlanis 1 txlanis 2 ecis1 3 decis1 4 tspis 5 - 6 bufis 7 - 8 rvcatis 9 ecis2 10 ecis3 11 ecis4 12 decis2 13 decis3 14 decis4 15 micis gl.isr gl.ier gl.mlsr3 gl.msier3 ar.bmis arbite r xmt serial decapsulato r rcv lan 1 mac 1 microport xmt lan su.lp1c su.wos su.wom vcat.rslsr[1-16] vcat.rsie[1-16] vcat.rrlsr vcat.rrsie ar.lqos ar.lqoim ar.wqos ar.wqoim ar.lqnfs ar.lqnfim ar.wqnfs ar.wqnfim ar.eqos ar.eqoim li.tvflsr li.tvfsrie pp.esmls[1-4] pp.esmie[1-4] pp.dmlsr[1-4] pp.dmlsie[1-4] vcat.risr su.mmcrsr (mac1) su.mmcrim (mac1) su.liqos rcv lan 2 mac 2 su.lp2c su.mmcrsr (mac2) su.mmcrim (mac2) su.liqos encapsulato r rcv vcat
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 43 of 375 8.9 forwarding modes and wan connections the path any given frame takes through the device can be determined by the contents of the frame, the port of entry, the user configured wan connections, and the user configured forwarding mode. 8.9.1 forwarding modes the set of rules that determine the route of frames betw een the ethernet interface(s) and wan data stream(s) is called the forwarding mode . the forwarding mode is selected in the gl.cr1 register. the five forwarding modes are listed below. the connections between the serial (wan) interfaces and the logical wan data streams described below are independent of these forw arding modes and will be described later. see table 8-4 for forwarding modes supported by each device. mode 1 - single ethernet port with priority forwarding mode 2 - per-ethernet-port forwarding with priority scheduling mode 3 - single ethernet port with vlan forwarding and priority scheduling mode 4 - per-ethernet-port forwarding, with vlan forw arding and priority scheduling within each vlan group mode 5 ? full vlan forwarding in both the lan-to-wan and wan-to-lan directions. forwarding mode 1 is single ethernet port with priority forwarding . in this mode, ethernet frames are segregated into up to four priority queues and transmitted in s eparate wan data streams. one example application is an ethernet switch that forwards its traffi c according to each frame?s priority enc oding, as in an ip dslam or isam that has a wan connection with a voip gateway on wa n interface #1, a video stream device on wan interface #2, and an internet pop on wan interface #3. forwarding mode 2 is per-ethernet-port forwarding with priority scheduling . in this mode, frames from each ethernet port are forwarded to their own group of four priority queues, generating two separate wan data streams with priority scheduled traffic. one example application is a leased li ne service for two independent ethernet subscribers. each subscriber pays its own leased line fe e and is guaranteed the full bandwidth of the wan line from end to end. this is the only mode that supports 1000mbps jumbo frames (must use single ethernet port operation). forwarding mode 3 is single ethernet port with vlan forwarding and priority scheduling . in this mode, ethernet frames are forwarded by vlan tag (vid) into up to four groups of four priority queues (wan groups) each. each wan group forms a separate wan data stream with prio rity scheduled traffic. one example application is an service router that is connected to four ip dslams vi a ds3s. in the lan-to-wan direction, vlan ids are used to distinguish the forwarding path while pr iority coding is used to schedule the selection of frames within a queue group. forwarding mode 4 is per-ethernet-port forwarding, with vlan fo rwarding and priority scheduling within each vlan group . in this mode, ethernet frames from each ethernet port are forwarded separately, by vlan tag, into two sets of four priority queues (wan groups) each. t he two wan groups form separate wan data streams with priority scheduled traffic. one example application is 2 leased lines for 2 independent ethernet subscribers (one route might go to chicago and the other to santa clara). vlan tagging is used to segregate the traffic bound for each route, and priority coding can be used to prov ide prioritized scheduling within a vlan group. forwarding mode 5 is full vlan forwarding in both the la n-to-wan and wan-to-lan directions . in this mode, ethernet frames from both ports can be forwarded by vlan tag (vid) to one of two shared wan groups. within each shared wan group, there are two sets of four strict priority queues. the tw o sets of strict priority queues are serviced with a round-robin algorithm. frames are then en capsulated by encapsulator #1 or #3. frames received from the wan side can be forwarded by vlan tag to either ethernet port. the lan-to-wan and wan-to-lan mappings are independent and can be configured separately . one example application is central office traffic grooming where the time sensitive voice and video are se gregated from a network and combined with other data streams of similar priority.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 44 of 375 figure 8-3. forwarding mode 1: single et hernet port with priority forwarding wan group 1 ethernet mac 1 serial port 1 lan queue 1 priority 1 transmit: the 16 serial ports are assigned to the four encapsulator wan groups with vcat.tcr3.tvgs receive: the 16 serial ports are assigned to the four decapsulator wan groups with vcat.rcr4.rvgs frames from the ethernet interface are forwarded to the lan queues based on priority (802.1p or dscp). wan ports lan ports wan insert queue qos bridge / filte r scheduler and transmit vcat/lcas processing receive vcat/lcas processor decapsulator #1 wan trap lan extract queue wan extract queue lan insert queue encapsulator 1 lan trap wan group 2 lan queue 5 priority 2 encapsulator 2 wan group 3 lan queue 9 priority 3 encapsulator 3 wan group 4 lan queue 13 priority 4 encapsulator 4 priority lookup table serial port 2 serial port 3 serial port 4 serial port 5 serial port 6 serial port 7 serial port 8 serial port 9 serial port 10 serial port 11 serial port 12 serial port 13 serial port 14 serial port 15 serial port 16 decapsulator #2 wan trap decapsulator #3 wan trap decapsulator #4 wan trap frames toward the ethernet interface are forwarded based on the order of receipt.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 45 of 375 figure 8-4. forwarding mode 2: one or two ethernet port forwarding with scheduling * note that forwarding mode 2 is the only forwarding mode available in the ds33x11. wan group 1 lan queue 4-p4 lan q ueue 3-p3 lan q ueue 2-p2 ethernet mac 1 serial port 1 lan queue 1 priority 1 transmit: the 16 serial ports are assigned to the four encapsulator wan groups with vcat.tcr3.tvgs receive: the 16 serial ports are assigned to the four decapsulator wan groups with vcat.rcr4.rvgs wan ports lan ports wan insert queue qos bridge / filte r scheduler and transmit vcat/lcas processing receive vcat/lcas processor decapsulator #1 wan trap ethernet mac 2 lan extract queue wan extract queue lan insert queue encapsulator 1 lan trap wan group 3 lan queue 12-p4 lan q ueue 11-p3 lan q ueue 10-p2 lan queue 9 priority 1 qos encapsulator 3 priority lookup table serial port 2 serial port 3 serial port 4 serial port 5 serial port 6 serial port 7 serial port 8 serial port 9 serial port 10 serial port 11 serial port 12 serial port 13 serial port 14 serial port 15 serial port 16 decapsulator #3 wan trap frames from the ethernet interfaces are forwarded to the wan groups based on physical port, then scheduled by priority (802.1p or dscp). frames toward the ethernet interface are forwarded based on the physical port.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 46 of 375 figure 8-5. forwarding mode 3: single ether net port with lan-vlan forwarding wan group 1 lan queue 4-p4 lan q ueue 3-p3 lan q ueue 2-p2 ethernet mac 1 serial port 1 lan queue 1 priority 1 transmit: the 16 serial ports are assigned to the four encapsulator wan groups with vcat.tcr3.tvgs receive: the 16 serial ports are assigned to the four decapsulator wan groups with vcat.rcr4.rvgs wan ports lan ports wan insert queue qos bridge / filte r scheduler and transmit vcat/lcas processing vlan (vid) lookup table receive vcat/lcas processor decapsulator #1 wan trap lan extract queue wan extract queue lan insert queue encapsulator 1 lan trap vlan processing wan group 2 lan queue 8-p4 lan q ueue 7-p3 lan q ueue 6-p2 lan queue 5 priority 1 qos encapsulator 2 wan group 3 lan queue 12-p4 lan q ueue 11-p3 lan q ueue 10-p2 lan queue 9 priority 1 qos encapsulator 3 wan group 4 lan queue 16-p4 lan q ueue 15-p3 lan q ueue 14-p2 lan queue 13 priority 1 qos encapsulator 4 priority lookup table serial port 2 serial port 3 serial port 4 serial port 5 serial port 6 serial port 7 serial port 8 serial port 9 serial port 10 serial port 11 serial port 12 serial port 13 serial port 14 serial port 15 serial port 16 vlan processing decapsulator #2 wan trap decapsulator #3 wan trap decapsulator #4 wan trap frames from the ethernet interface are forwarded to the wan groups based on vlan tag, then scheduled by priority frames toward the ethernet interface are forwarded based on the order of receipt.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 47 of 375 figure 8-6. forwarding mode 4: 1 ethernet port with port id and lan-vlan forwarding wan group 1 lan queue 4-p4 lan q ueue 3-p3 lan q ueue 2-p2 ethernet mac 1 serial port 1 lan queue 1 priority 1 transmit: the 16 serial ports are assigned to the four encapsulator wan groups with vcat.tcr3.tvgs receive: the 16 serial ports are assigned to the four decapsulator wan groups with vcat.rcr4.rvgs wan ports lan ports wan insert queue qos bridge / filte r scheduler and transmit vcat/lcas processing vlan (vid) lookup table receive vcat/lcas processor decapsulator #1 wan trap ethernet mac 2 lan extract queue wan extract queue lan insert queue encapsulator 1 lan trap vlan processing wan group 2 lan queue 8-p4 lan q ueue 7-p3 lan q ueue 6-p2 lan queue 5 priority 1 qos encapsulator 2 wan group 3 lan queue 12-p4 lan q ueue 11-p3 lan q ueue 10-p2 lan queue 9 priority 1 qos encapsulator 3 wan group 4 lan queue 16-p4 lan q ueue 15-p3 lan q ueue 14-p2 lan queue 13 priority 1 qos encapsulator 4 priority lookup table serial port 2 serial port 3 serial port 4 serial port 5 serial port 6 serial port 7 serial port 8 serial port 9 serial port 10 serial port 11 serial port 12 serial port 13 serial port 14 serial port 15 serial port 16 vlan processing decapsulator #2 wan trap decapsulator #3 wan trap decapsulator #4 wan trap frames from the ethernet interfaces are forwarded to the wan groups based on physical port, then by vlan tag, and are scheduled by priority (802.1p or dscp). frames toward the ethernet interface are forwarded based on physical port, in order of receipt.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 48 of 375 figure 8-7. forwarding mode 5: full lan-to -wan and wan-to-lan vlan forwarding wan group 1 lan queue 4-p4 lan q ueue 3-p3 lan q ueue 2-p2 ethernet mac 1 serial port 1 lan queue 1 priority 1 transmit: the 16 serial ports are assigned to the four encapsulator wan groups with vcat.tcr3.tvgs receive: the 16 serial ports are assigned to the four decapsulator wan groups with vcat.rcr4.rvgs wan ports lan ports wan insert queue qos bridge / filte r scheduler and transmit vcat/lcas processing vlan (vid) lookup table receive vcat/lcas processor decapsulator #1 wan trap ethernet mac 2 lan extract queue wan extract queue lan insert queue lan trap vlan processing wan group 3 lan queue 8-p4 lan q ueue 7-p3 lan q ueue 6-p2 lan queue 5 priority 1 qos wan group 2 lan queue 12-p4 lan q ueue 11-p3 lan q ueue 10-p2 lan queue 9 priority 1 qos wan group 4 lan queue 16-p4 lan q ueue 15-p3 lan q ueue 14-p2 lan queue 13 priority 1 qos priority lookup table serial port 2 serial port 3 serial port 4 serial port 5 serial port 6 serial port 7 serial port 8 serial port 9 serial port 10 serial port 11 serial port 12 serial port 13 serial port 14 serial port 15 serial port 16 vlan processing decapsulator #3 wan trap frames from mac 1 are sent to wan groups 1 or 2 based on vid. frames from mac 2 are sent to wan groups 3 or 4. all are scheduled by priority (802.1p or dscp) frames toward the ethernet interface are forwarded based on the vlan tag encapsulator 1 encapsulator 3 note: frames in each pair of wan groups are scheduled by a round-robin scheduler.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 49 of 375 the user may choose to disable unused features in a forwarding mode. in the forwarding modes with priority forwarding or priority scheduling, both 802.1p vlan pcp and dscp are supported. the user-programmable priority table is accessed through the su.ptc , su.ptaa , su.ptwd , su.ptrd , and su.ptsa registers. the priority and quality of service (qos) features of the device are discussed further in section 8.16. gigabit ethernet applications may only use forwarding modes that support 1 ethernet port (modes 1, 2, or 3). in all forwarding modes, vcat/lcas can be used to aggregate multiple physical serial ports for each wan group?s data stream, except on the devices in the product family that do not support vcat/lc as. more information on the use of vcat/lcas for link aggregation can be found in section 8.12. in the forwarding modes that use vlan vid tags, the device references a user-programmable lookup table to make forwarding decisions. through the su.vtc, su.vtaa, su.vtwd, and su.vtrd registers, the user must program a lookup table that maps up to 4096 vlan vid t ags each to one of the four wan groups in the lan-to- wan direction, and from the wan group s to the two ethernet interfaces in the wan-to-lan direction. more information on vlan mapping can be found in section 8.16. within each wan queue group, 802.1p vlan priority coding or dscp priority coding can be used to assign tr affic to 4 different priority queues. more information on priority forwarding and scheduling for qua lity of service can be found in section 8.16. table 8-4. forwarding modes supported by device forwarding mode ds33x161 ds33x81 ds33x41 ds33x11 ds33w11 ds33w41 ds33x42 DS33X162 ds33x82 1 no yes yes yes 2 yes yes yes yes 3 no yes yes yes 4 no no no yes 5 no no yes yes 8.9.2 wan connections each serial (wan) interface is mapped to a wan group through the vcat.tcr3(1-16) and vcat.rcr4(1-16) registers. a wan interface can only be assigned to one wan group. in devices in the product family that support vcat operation, if enabled, more than one wan interfac e can be assigned to a wan group. whenever a wan group has more than one member, vcat must be enabled for that group. a vcat enabled wan group can include up to 16 wan interfaces. more information on t he use of vcat/lcas for link aggregation can be found in section 8.12.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 50 of 375 8.9.3 queue configuration the starting and ending locations for each queue in ddr sd ram are user-configured. the address space of a 256 mbit ddr sdram is 24-bits, providing an address range covering 16m 16-bit words. to reduce the complexity of the user interface, only the upper 10 bits of each start/ end queue address are user-configured. this provides a minimum queue size granularity of 16k 16-bit words, or 32 kbytes. the 10-bit values programmed into the queue configuration registers can be multiplied by 32,768 in order to convert to bytes. each serial (wan) interface has an associated receiv e wan queue in external ddr sdram. the wan queues receive data from the wan interfaces and buffer it for proc essing. the user configures the size and location of these queues through control registers in the arbite r. starting wan queue addresses are configured in ar.wq1sa - ar.wq16sa , and ending addresses in ar.wq1ea - ar.wq16ea . when using vcat/lcas, the wan queues are also used for differential delay compen sation between members of a vcg. the user-configured depth of these queues should provide for approximately 200 ms of data at the wa n line rate. this translates to approximately 10mb at a 52mbps rate, and 300kb at 1.544mbps. while it is po ssible to configure larger wan queues, note that limitations of the vcat protocol only allow the resolution of 200ms at the line rate, and aliasing may occur at larger wan queue depths. data from the lan interface is received into an internal buffer monitored by the su.liqos.liqos bits. it is then immediately processed and placed into one of 16 lan queu es in external sdram, based on the forwarding mode and information within the frame. starting wan queue addresses are configures in ar.lq1sa - ar.wq16sa and ending addresses are configured in ar.lq1ea - ar.lq16ea . the user defines a lan queue threshold (watermark) that is used to trigger ethernet flow control or device interrupts in the ar.lqw register. because wan standards do not have a method for interactive flow-control, the wan queues do not have user-programmable watermark. the device provides overflow status for the wan queues in ar.wqos and for the lan queues in ar.lqos . the device provides an indication that frame discarding has been triggered due to the level of the wan queues in ar.wqnfs . the interrupt operation related to these functions is further defined in section 8.8. there are also four special-purpose external sdram queues used for frame insertion and extraction. the user configures the size and location of these through control r egisters in the arbiter. the lan insert queue is defined by ar.liqsa and ar.liqea . the lan extract queue is defined by ar.leqsa and ar.leqea . the wan insert queue is defined by ar.wiqsa and ar.wiqea . the wan extract queue is defined by ar.weqsa and ar.weqea . overflow status for the extraction queues is provided in ar.eqos an additional portion of the external sdram must be alloca ted for the bridge/filter function when in use. the 4k x 6-byte table used for da lookup operations w ill be constructed at the location in the ar.bftoa register. the device does not provide error indication if the user creates a connection and queue that overwrites data for another connection queue. the user must take care in setting the queue sizes. the lan and wan queue pointers must be reset before tra ffic flow can begin. if this procedure is not followed, incorrect data may be transmitted. the proper pr ocedure for setting up a connection follows: ? set up the queue sizes for both lan and wan queues. ? set up the lan queue threshold and associated interrupt enables if desired. ? reset the pointers for the associated queues ? enable the associated ports. ? if a port is disconnected, reset the queue pointer after the disconnection. each queue can be individually reset as needed through the starting address register for that queue. all queue pointers can be reset simultaneously through the ar.mqc register. this register also configures the behavior of the wan frame insertion. two scheduling algorithms can be used for prioritizing traffic to be transmitted from the lan queues to the wan interface: strict priority and weight ed round-robin (wrr). wrr scheduling is available only in forwarding mode 2, with one ethernet port. this is configured in the ar.lqsc register.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 51 of 375 8.10 bandwidth capabilities (throughput) all devices in the product family support approximately 416mbps aggregate throughput. however, on the high-port count devices with dual ethernet interfaces (the DS33X162 and ds33x82), it is necessary to conform to certain constraints when interfacing with t3/e3 wan lines. these constraints do not apply for t1/e1 transport. also, these constraints do not apply to devices other than the DS33X162 and ds33x82. table 8-5. maximum number of t3/e3 lines per encapsulator (DS33X162 and ds33x82 only) enabled encapsulators ds33x82 DS33X162 (with 8 ports enabled) DS33X162 (with more than 8 ports enabled) 1 8 t3/e3 8 t3/e3 not applicable 2 5 t3/e3 5 t3/e3 3 t3/e3 3 3 t3/e3 3 t3/e3 2 t3/e3 4 2 t3/e3 2 t3/e3 2 t3/e3 attempting operation of the DS33X162 or ds33x82 outside of these constraints may cause data loss. if the user wishes to operate outside of the device?s designed cap abilities, it is recommended that the user evaluate the device performance under t he specific application conditions and deter mine if the measured performance is acceptable. note that the wan groups support the following rates: ? maximum data rate for wan groups 1 and 2 = up to 416mbps total (group 1 + group 2 418mbps) ? maximum data rate for wan groups 3 and 4 = 180mbps each note that the individual wan ports support the following rates: ? maximum line rate for wan ports 1-8 = 52mbps each ? maximum line rate for wan ports 9-16 = 2.044mbps each
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 52 of 375 8.11 serial (wan) the serial interfaces support time-division multiplexed, se rial data i/o up to 52mbps. the serial interface receives and transmits encapsulated ethernet frames, and consists of a physical serial port with a gfp/x.86/hdlc/chdlc engine. each physical interface consists of a data pin, cloc k pin, and a synchronization pin in both the transmit and receive directions. the serial interface can operate with a gapped clock, and can be connected to a framer, electrical liu, optical transceiver, or t/e-carrier transceiver for wan transm ission. the serial interface can be seamlessly connected to the maxim t1/e1/j1 framers, li ne interface units (lius), and single-chip transceivers (scts). the interface can also be s eamlessly connected to the maxim t3/e 3/sts-1 framers, lius, and scts to provide t3, e3, and sts1 connectivity. receive features: user configurable receive serial ports (up to 16) user configurable receive voice port(s) (ds33w41/ds33w11 only) programmable clock inversion serial data is byte-aligned with reference to receive frame sync (msb follows frame sync) demuxes voice traffic from t1/e1/xdsl (maximum of 16 ds0s per port) and output on voice port (ds33w41/ds33w11 only) buffers demuxed voice traffi c and realign with rvsync and rvclk (ds33w41/ds33w11 only) reports loss of rclkn capability of rdata to tdata loopback reports fifo underflow/overflow transmit features: data is byte-aligned to tmsync/tsync (msb follows tmsync/tsync) tmsync/tsync is an input that may be lined up with the framing overhead of the t1/e1/t3/e3 frame or programmable to be expected three cycles early. user configurable transmit ports (up to 16) user configurable transmit voice port(s) (ds33w41/ds33w11 only) programmable clock inversion muxes voice traffic to t1/e1/xdsl (ds33w41/ds3 3w11 only, ports 1-4) buffers voice traffic(maximum 16 ds0s per port) to mux in with frame data and retime to tmclk/tclk and tmsync/tsync (ds33w41/ds33w11 only) reports loss of tclk capable of tdata to rdata loopback (replaces rclk with tmclk/tclk) 8.11.1 voice support (ds33w11 and dw33w41 only) voice demuxing is done on frame sync boundaries, with a programmable number of octets (with a maximum of 16) to be demuxed to the voice fifo. these are the octets immediately following the frame sync boundary. voice octets are read from voice fifo one frame later after written to fifo. voice muxing occurs on frame sync boundaries and a prog rammable number of octets(with a maximum of 16) are read from the voice fifo. these octets will appear on tdata immediately following the tmsync/tsync signal.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 53 of 375 8.12 link aggregation and link c apacity adjustment (vcat/lcas) virtual concatenation (vcat) allows information to be tr ansmitted over up to 16 aggregated wan links. the vcat function aligns all members of the vcg to the link wi th the most transmission delay. the information on all members of the vcg must be buffered until the last data is received from the link with the most transmission delay. the maximum differential delay allowed between the link with the most delay and the link with the least delay is 200 ms. note that the queue size is user-programmed and could potentially be configured for values larger than 200 ms of data. in vcat mode, the maximum recommended queue size is 200 ms worth of data. if the user configures a queue size larger than 200ms while in vcat mode, errors may occur due to aliasing. note that link aggregation is not possible using the ds33x11 and ds33w11 , but the insertion of vcat overhead is supported on these devices. vcat features: ? 4 vcgs for the DS33X162/x82, 2 vcgs for the ds33x42, 1 vcg for t he ds33x161/x81/x41/w41 ? max differential delay = 200 ms ? receive and transmit are independent (asymmetrical support) ? user programmable configuration of wan ports used for vcg ? supports virtual concatenation of up to 8 t3/e3 or 16 t1/e1 ? rclks of a vcg must be frequency locked. ? all tmclks/tclks used for a vcg must be frequency locked. table 8-6. vcat/lcas control frame for t1/e1 concatenation overhead octet definition bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 control packet mfi1 mst (1-4) 1 0 0 0 mst (5-8) 1 0 0 1 0 0 0 rs-ack 1 0 1 0 reserved (0000) 1 0 1 1 reserved (0000) 1 1 0 0 reserved (0000) 1 1 0 1 reserved (0000) 1 1 1 0 sq bits 1-4 1 1 1 1 mfi2 msbs (1-4) 0 0 0 0 mfi2 lsbs (5-8) 0 0 0 1 ctrl 0 0 1 0 0 0 0 gid 0 0 1 1 reserved (0000) 0 1 0 0 reserved (0000) 0 1 0 1 c 1 c 2 c 3 c 4 0 1 1 0 c 5 c 6 c 7 c 8 0 1 1 1
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 54 of 375 8.12.1 vcat/lcas control frame for t3/e3 table 8-7. vcat/lcas control frame for t3/e3 concatenation overhead octet definition bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 control packet mfi1 mst (1-4) 1 0 0 0 mst (5-8) 1 0 0 1 0 0 0 rs-ack 1 0 1 0 reserved (0000) 1 0 1 1 reserved (0000) 1 1 0 0 reserved (0000) 1 1 0 1 reserved (0000) 1 1 1 0 0 sq bits 1-3 1 1 1 1 mfi2 msbs (1-4) 0 0 0 0 mfi2 lsbs (5-8) 0 0 0 1 ctrl 0 0 1 0 0 0 0 gid 0 0 1 1 reserved (0000) 0 1 0 0 reserved (0000) 0 1 0 1 c 1 c 2 c 3 c 4 0 1 1 0 c 5 c 6 c 7 c 8 0 1 1 1
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 55 of 375 8.12.2 vcat/lcas confi guration and operation vcat/lcas setup requires an external micro to issue an instruction to setup and tear down the imux function. the microprocessor can turn off links that are not par ticipating. once any changes to the transmit vcat configuration are made, a zero-to-one transition on vcat.tcr1.tload is required in order to load the updated configuration. 8.12.2.1receive vcat initialization 1. configure the vcg frame mode via vcat.rcr1.t3t1 2. configure vcat.rcr3 with the number of members per vcg. 3. assign each port to the appropriate vcg via vcat.rcr4.rvgs[2:0] and vcat.rcr4.rpa . 4. enable the receive vcat blocks via vcat.rcr1.rvblken and vcat.rcr1.rvenn . 5. clear the fifo reset in vcat.rcr4 . 6. if needed, enable lcas via vcat.rcr2.le[4:1]. 8.12.2.2transmit vc group in itialization ? lcas enabled 1. assign each port to the appropriate vcg via vcat.tcr3.tvgs[2:0] and vcat.tcr3.tpa . 2. assign the sequence number to each port via vcat.tcr3.sq[3:0] . 3. configure vcat.tcr2 with the number of members per vcg. 4. configure the vcg frame mode via vcat.tcr1.vnfm[1:0] . 5. write the lcas control word via vcat.tlcr8.ctrl[3:0] to idle for participating links. 6. enable lcas through vcat.rcr2.le[4:1] . 7. enable the transmit vcat block via vcat.tcr1.tvblken . 8. initiate a zero-to-one transition on vcat.tcr1.tload in order to load the configuration. 8.12.2.3transmit vc group initialization (lcas disabled) 1. assign each port to the appropriate vcg via vcat.tcr3.tvgs[2:0] and vcat.tcr3.tpa . 2. assign the sequence number to each port via vcat.tcr3.sq[3:0] . 3. configure each vcg frame mode via vcat.tcr1.vnfm[1:0] . 4. configure vcat.tcr2 with the number of members per vcg. 5. enable the transmit vcat block via vcat.tcr1.tvblken . 6. initiate a zero-to-one transition on vcat.tcr1.tload in order to load the configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 56 of 375 8.12.3 link capacity adjust ment scheme (lcas) the link capacity adjustment scheme (lcas) provides the capability to add and remove members from a vcat vcg. if lcas is enabled via vcat.rcr2.le[3:0] , the receive lcas block will extract all lcas frame information from the vcat overhead. the lcas stat us registers report the ctrl, gid, rs-ack, and mst fields of the vcat frame. the lcas ctrl field communicates the intent to add or remove a member from the group. the device coordinates the addition or removal of links from the gr oup of active members so that changes are hitless. the transmit mst values are automatically controlled by the device by default. optionally, this function can be controlled by user software via the vcat.tlcr3 ? vcat.tlcr6 registers. the transmit mst field communicates the condition of the line (e.g., an lom alarm), the re ception of an add command ( and subsequent successful alignment to the vcg), and the reception of a remove command. to enable transmit lcas, follow the in itialization steps outlined in section 8.12.2.2. note that the vcat.tlcr8.ctrl[3:0] bits should be initialized with a ctrl co mmand of idle. all cha nges to the ctrl[3:0] register bits must be followed with a zero-to-one transition on vcat.tcr1.tload for the change to take effect. receive lcas functions: ? aligns all members of the vcg ? reports relevant fields and alarms to status registers ? automatically transmits mst back to the s ource (manual control also configurable) transmit lcas functions: ? outputs ctrl, mst, gid, rs-ack to be inserted into vcat overhead ? gid prbs generator and insertion ? user-configured gid insertion ? crc generation and insertion 8.12.3.1example lcas operation 1. initial ctrl command of idle, sq value = max (16 for t1/e1, 8 for t3/e3) 2. addition of member: a. send add command, change sq value to 1+ sq value(active link with the highest sq) b. wait for mst=ok on receive lcas ( vcat.rlsr1 register) c. send eos on this port; port that was sending eos now sends norm 3. removal of member a. change command from norm/eos to idle; change sq value to max; reorder other active members? sq; if change was from eos to idle, then next highest member changes from norm to eos 4. response to receive lcas reporting mst=fail a. if the receive lcas reports that a mst value changed from ok to fail, the transmit lcas should send dnu on that port. b. the sq value remains the same. c. if the member that changes to dnu was eos, eos must be assigned to the member next in line.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 57 of 375 8.12.4 alarms and condition s related to vcat/lcas the latched status bits for the vcat/lcas sequence ( vcat.rslsr.sql ), control ( vcat.rslsr.ctrl ) and rs-ack ( vcat.rslsr.rsackl ) bits can be used to generate device in terrupts on a change of state. the latched loss of multiframe sync ( vcat.rslsr.loml ), realign ( vcat.rrlsr.realign[1-4] ) and differential delay ( vcat.rrlsr.dde[1-4] ) bits can be used to generate an interrupt upon transition from the inactive (normal) to the active (alarm) state. if the user?s application requires an indication of the transition from the active to inactive condition, the host processor should poll the (non-latched) status bits to determine when the alarm becomes inactive. 8.13 arbiter/buffer manager the arbiter manages the transport between the ethernet and serial ports. it is responsible for queuing and dequeuing frames to a single external sdram. the arbiter handles reques ts from the packet processor and mac to transfer data to and from the sdram. for more informat ion of how the arbiter settings affect qos, see section 8.16. for more information on configuring the arbite r?s interactions with the sdram queues, see section 8.9.3.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 58 of 375 8.14 flow control in some applications, flow control may be required to en sure that data queues do not overflow and frames are not dropped. the device allows for optional ieee 802.3 compliant flow control. th ere are 2 basic mechanisms of flow control: ? in half duplex mode, a jam sequence is sent that c auses a collision detection at the far end. the collision causes the transmitting node to reduce the rate of transmission. ? in full duplex mode, flow control is initiated by the receiving node sending a pause frame. the pause frame contains a time parameter that determines the pause timeout to be used by the transmitting node. several conditions can initiate the flow control mechanism: ? flow control can be initiated by a lan queue filling above the watermark programmed in ar.lqw . flow control for each lan queue is independanty enabled in the su.lqxpc register. note that the lan queues are external ddr sdram buffers used to store data that has arrived on the mii/rmii/gmii interface(s) and has been proc essed by the receive mac. ? flow control can be initiated by the cir policing function. more information on this function can be found in section 8.21. ? transmission of a pause frame can be m anually initiated by writing a 1 to su.macfcr.fcb . the pause time value that is transmitted in outgoi ng pause frames is user-programmable in the su.macfcr register. note that pause control frame tr ansmission must also be enabled with the su.macfcr.tfe bit. pause frame receipt must be enabled with su.macfcr.rfe . although not commonly used, unicast pause frame reception can be enabled with su.macfcr.up . the watermark value programmed into ar.lqw is in units of memory from the top of the queue, thus a larger value in ar.lqw indicates that more memory will remain available in t he queue when flow cont rol is exerted. note that in order to use flow control, the minimum lan queu e size is 2 frames (of maximum size) deep and the lan queue watermark threshold ( ar.lqw ) must be set to allow a minimum of 1 frame of maximum size to be received after the threshold is crossed. if the watermark is set too close to the top of the queue to allow time for the remote node to respond, automatic flow control will not be effective. in some applications, ethernet flow control can interfere with higher-layer flow cont rol protocols. for example, tcp/ip flow control depends on lost frames in order to detect when it has exceeded a sy stem?s capabilities. tcp/ip flow control uses an increasing flow rate until lost frames are detected, at which point a back-off & resend algorithm is used, based on the number of lost fr ames until a steady stream is maintained. if no frames are lo st, tcp/ip will continue attempting to increase the flow rate. if tcp/ip fl ow control is used in conjunction with ethernet flow control, the results may be undesirable for some applications. the system architect should carefully study this topic to determine if the system in design should use ethernet flow control or frame discarding. the DS33X162 family of devices support bot h flow control and frame discarding.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 59 of 375 8.14.1 full duplex flow control automatic flow control is governed by the lan queue high watermark in ar.lqw , and is enabled per lan queue in the su.lqxpc register. this allows the user to enable or di sable flow control for each of the four mapped pcp/dscp priorities. when the lan queue threshold is ex ceeded on which flow control is enabled, the device will send a pause frame with the timer value programmed in su.macfcr.pt[15:0] when in full duplex, or a jamming signal in half duplex. more information on configuring the queues, see section 8.9.3. also see the su.macfcr register definition for recommended flow control settings. the pause frame causes the distant transmitter to ?pause fo r a time? before starting transmission again. the device will send a pause frame as the queue has crossed the threshold defined in ar.lqw . the pause control frame is retransmitted every 16.4us, 164us, or 1.64ms, depending on the settings in su.macfcr.plt . the receive queue could keep growing if the round trip delay is greater th an the pause time. pause control will only take care of temporary congestion it does not take care of systems wh ere the traffic throughput is too high for the queue sizes selected. if the flow control is not effective the receive queue will eventually overflow. this is indicated in su.liqos . if the receive queue is overflowed any new frames will not be received until the overflow condition is corrected.. the user has the option of not enabling automatic flow control. in this case the thresholds and corresponding interrupt mechanism to send pause frame by writing to the fcb bit in the mac flow control register su.macfcr . this allows the user to set not only the watermarks but also to decide when to send a pause frame or not based on watermark crossings. on the receive side the user has control over whether to respond to the pause frame sent by the distant end ( su.macfcr.rfe bit). on the transmit queue the user has the option of setting high and low thresholds and corresponding interrupts. there is no automatic flow control mechanism for data received from the serial side waiting for transmission over the ethernet in terface during times of heavy ethernet congestion. 8.14.2 half duplex flow control half duplex flow control functions like full duplex fl ow control, but a jamming sequence is used to exert backpressure on the transmitting node rather than pause control frames. the receiving node jams the first 4 bytes of a frame that are received from the mac in order to cause a collision detection at the distant end. in both 100mbps and 10mbps mii/rmii modes, 4 by tes are jammed upon recept ion of a new frame. no te that the jamming mechanism does not jam the fr ame that is being received during the wate rmark crossing, but will wait to jam the next frame after the ar.lqw is crossed. if the queue remains above t he threshold, received frames will continue to be jammed. this jam sequence is stopped when the queue falls below the threshold in ar.lqw .
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 60 of 375 8.15 ethernet interfaces the ethernet interface allows for direct connection to et hernet phys. the interface consists of a dual 10/100mbps mii/rmii interface or a single 1000mbps gmii interface and associated ethernet macs. in gmii operation, the interface contains 23 signals with a re ference clock of 125mhz. in dual mii opera tion, each interface contains of 12 signals and uses a clock reference of 25mhz. in rmii operat ion, the interface contains 7 signals with a reference clock of 50mhz. the device can be confi gured for gmii, mii, or rmii operation with the gl.cr1.p1spd , gl.cr1.p2spd, su.maccr.gmiimiis bits and the rmii_sel input pin. in dte mode of operation, the tx_clk and rx_clk signals are generated by the phy and are inputs. the data received from the mii, rmii, or gmii interface(s) is processed by internal ieee 802.3 compliant ethernet macs. the user can configure a maximum receive fram e length beyond which the mac discards the complete frame. the maximum frame size can be configured in the su.mpl register to any value up to 10240 bytes. sizes over 2048 bytes are considered ?jumbo? frames. for more information on jumbo frame support requirements, see table 10-5. the maximum frame length (in bits) is the number specified in su.mpl multiplied by 8. the frame length calculation is shown below in figure 8-8. the frame length includes only destination address, source address, vlan tag (2 bytes), type length field, data and crc32. note that the calculation used for maximum frame size results in a different value than the 802.3 type/length field shown in the figure. figure 8-8. ieee 802.3 ethernet frame preamble sfd destination adrs source address type / length data crc32 7 1 6 6 2 46-1500 4 max frame length the distant end will normally reject the sent frames if jabber timeout, loss of carrier, excessive deferral, late collisions, excessive collisions , under run, deferred or collision errors oc cur. transmission of a frame under any of these errors will be logged by the mac management count ers. the device provides user the option to not automatically retransmit the frame if any of the errors have occurred through the mac?s su.maccr.drty bit. frames received with errors are usually rejected by t he device. more information on the ethernet mac functions can be found in section 8.19.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 61 of 375 table 8-8. configuration recommendations for maximum frame length maximum frame length (bytes) su.mpl su.maccr.wdd su.maccr.jd su.maccr.jfe 1518 1518 0 0 0 2048 2048 0 0 0 9018 9018 1 1 1 (half-duplex) 0 (full-duplex) 10240 10240 1 1 1 (half-duplex) 0 (full-duplex) table 8-9. selection of mac interface modes for port 1 function rmii_sel pin dcedtes pin gmiimiis bit p1spd bit gmii 0 0 0 don?t care rmii 1 0 1 0 for 10mbps 1 for 100mbps mii (dte mode) 0 0 1 0 for 10mbps 1 for 100mbps mii (dce mode) 0 1 1 0 for 10mbps 1 for 100mbps table 8-10. selection of mac interface modes for port 2 function rmii_sel pin dcedtes pin gmiimiis bit p1spd bit rmii 1 0 1 0 for 10mbps 1 for 100mbps mii (dte mode) 0 0 1 0 for 10mbps 1 for 100mbps mii (dce mode) 0 1 1 0 for 10mbps 1 for 100mbps
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 62 of 375 8.15.1 gmii mode gmii interface operates synchronously from the exter nal 125mhz reference, and 23 signals are required. the following figure shows the gmii architecture. note that dce mode is not supported for gmii mode and that gmii is valid only for full duplex operation. figure 8-9. example configuration of gmii interface (dte mode only) transmit receive txd[7:0] tx_en1 rx_err1 rxd[7:0] rx_dv1 ds33x/w mac gmii phy rx_clk1 rx_crs1 gtx_clk tx_err1 mdio control mdc
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 63 of 375 8.15.2 mii mode the ethernet interface can be configured for rmii operation by setting the hardware pin rmiimiis low. mii interface operates synchronously from the external 25mhz reference (ref_clk ). the following figure shows the mii architecture. figure 8-10. example configuration as dte connected to an ethernet phy in mii mode mac rxd[3:0] rxd[3:0] rx_clk rx_clk rx_err rx_err rx_crs rx_crs col_det col_det ethernet phy tx_en tx_en mdc mdio txd[3:0] txd[3:0] tx_clk wan dce dte tx_clk mdio mdc rxdv rxdv rx rx tx tx arbiter
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 64 of 375 table 8-11. mii mode options mode/speed functions 10mbps full duplex dte mode with no flow control while in full duplex, mii dte mode, both the receive and transmit mii clocks are inputs. 100mbps full duplex, dte mode with flow control in full duplex dte mode the clocks are expected from the phy. the flow control for a full duplex operation is using control frames. if the mac receives a pause command the transmitter is disabled for the time specified in the pause command. the pause command has a multicast address 01-80-62-00-00-01. the mac can also initiate a pause control frame with su.macfcr.fcb . the duration field in the pause control frame is determined by settings in the mac flow control register 100mbps full duplex, dte mode with no flow control ? 100mbps full duplex dce mode with flow control in full duplex dce mode, the clocks ar e provided by the device. the flow control for a full duplex operation is using control frames. if the mac receives a pause command the transmitter is disabled for the time specified in the pause command. the pause command has a multicast address 01-80-62-00-00-01. the mac can also initiate a pause control frame with su.macfcr.fcb . the duration field in the pause control frame is determined by settings in the mac flow control register
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 65 of 375 8.15.3 dte and dce mode when in 10/100 mode, the ethernet mii interface(s) can be configured for dce or dte mode. when configured in dte mode, direct connection can be made to ethernet phys . in dce mode, the mii interface can be connected to mii mac devices other than an ethernet phy, such as ethernet switch devices. the dte/dce connections in mii mode are shown in the following 2 figures. in dce mode, the transmitter is connected to an external receiver and receiver is connected to an external mac transmitter. the selection of dte or dce mode is done by the hardware pin dcedtes. dce mode is not valid for gbe (gmii) operation. figure 8-11. example configuration as a dce in mii mode mac txd[3:0] rxd[3:0] tx_clk rx_clk tx_err rx_err tx_en rx_crs col_det col_det dte dce tx_en rxdv mdc mdio txd[3:0] rxd[3:0] tx_clk wan mac rx_clk rxdv rx_crs mdio mdc rx tx tx rx arbiter
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 66 of 375 8.15.4 rmii mode the ethernet interface can be configured for rmii oper ation by setting the hardware pin rmiimiis high. rmii interface operates synchronously from the external 50mhz reference (ref_clk). only 7 signals are required. the following figure shows the rmii architecture. note that dce mode is not supported for rmii mode and rmii is valid only for full duplex operation. figure 8-12. rmii interface (dte mode only) transmit mac receive mac txd[1:0] tx_en ref_clk rxd[1:0] crs_dv ds33x mac - rmii phy rmii to mii tx_en txd[3:0] tx_err tx_clk crs rx_dv rxd[3:0] rx_er rx_clk
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 67 of 375 8.16 quality of service (qos) features the device contains several features designed to provide quality of service (qos). these features include virtual lan (vlan) forwarding and priority scheduling/forwarding supporting both vlan 802.1p and dscp. the device also includes features for congestion avoidance and congestion management. information on congestion avoidance using the integrated cir can be found in section 8.21. information on congestion management using ethernet flow control can be found in section 8.14. vlan forwarding is used to separate traffic into different stream s or combine traffic from multiple sources into a single stream, while priority scheduling is used to prioritize traffic waiting in queue for wan transmit bandwidth to become available. note that prio rity scheduling is different than priority forwarding . priority forwarding is a technique used to separate traffic of various priority leve ls onto physically separate wan connections. the use of vlan forwarding, priority scheduling, and priority forw arding is determined by t he forwarding mode of the device. more information on the availabl e forwarding modes can be found in section 8.9. within the data stream for each wan queue group, 802.1p vlan priority coding or dscp priority coding can be used to assign traffic to 4 different priori ty queues as discussed in the following sections. 8.16.1 vlan forwarding by vid (ieee 802.1q) the vlan id (vid) is a 12-bit fiel d that is found beginning in the 15 th byte of vlan tagged ethernet frames. the format of the ieee 802.1q vlan tagged frame is shown in figure 8-13. the device uses a 4 kilobyte user- configured ?vlan table? to translate vlan tag informati on into forwarding, trapping, or discarding decisions. for more details on vlan table programming, see section 8.16.2. all frames received on the ethernet interfaces are inspec ted for a vlan id (lan-vlan id) value. the vlan table settings for each of the 4096 lan-vlan ids are used to fo rward each frame to one of the four wan groups, to discard the frame, or to extract (trap) the frame. only when operating in forwardi ng modes 3, 4, and 5 (as defined in section 8.9), can frames be forwarded to one of the four wan groups as assigned in the vlan table. all 12-bit lan-vlan ids that are translated to the same wan group are considered part of the same lan-vlan group . note that lan-vlan id trapping must be assigned to an ethernet port with the su.lpm.leeps bit, and enabled with the su.lpm.levit bit. all frames received on the wan interfaces are inspected for a vlan id (wan-vlan id) value. ). the vlan table settings for each of the 4096 wan-vlan ids are used to forward each frame to one of the ethernet ports, to discard the frame, or to extract (trap) the frame. only when operating in forwarding mode 5 (as defined in section 8.9), can frames be forward to one of the ethernet ports by their vlan id value. all 12-bit lan-vlan ids that are translated to the same ethernet interface are considered part of the same wan-vlan group . note that wan- vlan forwarding is only applicable when operating in forw arding mode 5. also note that wan-vlan id trapping must be assigned to a specific wan group with the su.wem.weds bits and enabled with the su.wem.wevit bit. the lan-vlan configuration, used to specify the actions for vlan id values in frames received on the ethernet interfaces (lan-to-wan direction), ma y be unrelated to the wan-vlan config uration, used to specify the actions for vlan id values for frames received on the wan interface (wan-to-lan direction). although there may be vlan tags in both data stream directions (lan-to-wan and wan-to-lan), the functionality of the device does not require a symmetrical vlan function. the lan-vlan forwarding and the wan-vlan forwarding may be used independently of each other.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 68 of 375 8.16.2 programming the vlan id table a 4 kilobyte user-configured ?vlan table? is used to tran slate vlan tag information from each received frame into forwarding, trapping (frame extracti on), or discarding decisions. each address in the table corresponds to a specific vlan id (vid) value from 0 to 4095 , and the bit settings at each address relate to actions taken when a frame containing the corresponding vlan id value is detected. the vlan table is configured through the su.vtc, su.vtaa, su.vtwd, and su.vtrd registers. within each address location in the vlan table, two bits of data determine the actions taken for frames received on the wan interfaces with vlan ids matching the table address value, and four bits determine actions taken on frames received on the lan interfaces with vlan ids matc hing the table address value. the 4k x 2 bit space used for wan functions is referred to as the wan-vlan table . the 4 k x 4 bit space used for lan functions is referred to as the l an-vlan table . the user can also configure a default ?no vlan detected? value in the su.lnfc register to indicate what should be done with frames that do not have a vlan tags. the user may indicate the same forwarding location as one of the other vlan groups, or it can be used to indicate an independent process or location. for example, the user may indicate to discard untagged frames, while vlan tags 0 through 4094 are forwarded to the 4 wan groups and vlan tag 4095 is forwarded to the lan extract queue. to reset the vlan table: 1) write su.vtc = 05h to ensure a 0-1 transition on su.vtc.ci and enable the vlan table. 2) write su.vtc = 07h. 3) read su.vtsa.vtis until = 1. to program the vlan table: 1) write su.vtaa = 00h in order to begin configuration at vid 00h . 2) 4096 times, write the value of su.vtwd for the desired action for each vid value. to verify the vlan table: 1) write su.vtaa = 00h in order to begin verification at vid 00h . 2) 4096 times, read the value of su.vtrd register and verify the value. the lan-vlan id frame extraction trap must be assigned to an ethernet port with the su.lpm.leeps bit, and enabled with the su.lpm.levit bit. the wan-vlan id frame extraction trap must be assigned to a specific wan group (decapsulator) with the su.wem.weds bits and enabled with the su.wem.wevit bit. in order to enable the vlan processing functions in each port, the su.lp1c.lp1etf[2:1] or su.lp2c . lp2etf[2:1] bits must be properly configured. when the vlan processing functions are enabled, incoming frames are inspected for vlan information. the vlan protocol id must match the value programmed in su.lqtpid . frames with alternate vlan pids are processed as ?untagged?. in the wan-to-lan direction, the corresponding function is performed in su.wetpid .
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 69 of 375 8.16.3 priority c oding with vlan tags (ieee 802.1p) the ieee 802.1q vlan tagging standard allocated room for a priority code that was later defin ed by the ieee 802.1p standard. ieee 802.1p eventually became part of ieee 802.1d. with priority scheduling or priority forwarding enabled, t he priority value is inspected as each frame arrives on the ethernet interfaces. for ieee 802. 1p priority coding, the prio rity is located in the 15 th byte of the ethernet frame. the format of the ieee 802.1p vlan tagged frame is shown in figure 8-13. a user-programmed priority table is used to translate the 3-bit 802.1p priority value into one of four priority levels for each ethernet interface. the received pcp value is used as the address for the priority table lookup operation. the priority levels correspond to four separate queues. in priority forwarding (forwa rding mode 1), the four queues are in separate wan groups. in priority scheduling operation, each wan gro up contains a set of four priority queues. these queues are collectively referred to as lan queues in other portions of this document. the priority mode (802.1p, dscp, or none) for each ethernet port can be independently selected using the su.lp1c and su.lp2c registers. see section 8.16.6 for more information on programming the priority table. figure 8-13. ieee 802.1q and 802.1p field format ethernet byte # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 2 3 4 5 6 destination address (da) 7 8 9 10 11 12 source address (sa) 13 8 (hex) 1 (hex) 14 0 (hex) 0 (hex) 15 3 bit pcp priority cfi 11 4 bits of vlan id 8 16 7 8 bits of vlan id 0 17 ethernet type / length (msb) 18 ethernet type / length (lsb) 19+ < data unit >
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 70 of 375 8.16.4 priority coding with mu ltiple (q-in-q) vlan tags device operation with multiple vlan tags is similar to operation with a single vlan tag. the ethernet q-in-q format is similar to the case outlined above, except that a sec ond vlan tag is inserted after the ethernet sa field. the format of the vlan q-in-q tagged frame is shown in figure 8-14. both vlan tags include a pcp (user priority) value and a vlan id. the device only makes forw arding and scheduling decisions using the ?outer-most? vlan tag located in ethernet bytes # 13-16, and ignores additional tags. the user can configure an alternate wan-vlan q-in-q or vlan tag protoc ol id (tpid) that is used instead of the default value of 8100 in the su.wetpid register. the user can configure an alternate lan-vl an q-in-q or vlan tag protocol id (tpid) that is used instead of the default value of 8100h in the su.lqtpid register. some additional common tpids are 9100, 9200 and 88a8. see section 8.16.6 for more information on programming the priority table. figure 8-14. vlan q-in-q field format ethernet byte # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 2 3 4 5 6 destination address (da) 7 8 9 10 11 12 source address (sa) 13 8 (hex) 1 (hex) 14 0 (hex) 0 (hex) 15 3 bit pcp priority cfi 11 4 bits of vlan id 8 16 7 8 bits of vlan id 0 17 8 (hex) 1 (hex) 18 0 (hex) 0 (hex) 19 3 bit pcp priority cfi 11 4 bits of vlan id 8 20 7 8 bits of vlan id 0 21 ethernet type / length (msb) 22 ethernet type / length (lsb) 23+ < data unit >
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 71 of 375 8.16.5 priority c oding with dscp the ietf rfc2474 (differentiated services) defines a la yer-3 alternate to 802.1p priority coding, known as differentiated services code point (dscp) . dscp is composed of a 6-bit value located in the second byte of the ip header. when priority scheduling or priority forwarding are enabled, the priority value is inspected as each frame arrives on the ethernet interfaces. the format of the dscp tagged frame is shown in figure 8-15. the device supports dscp priority carried in ipv4 or ipv6 packets. a user-programmed priority table is used to translate the 6-bit dscp priority into one of four priority levels for each ethernet interface. the received pcp value is used as the address for the priority table lookup operation. the priority levels correspond to four separate queues. in priority forwarding (forwarding mode 1), the four queues are in separate wan groups. in priority scheduling operation, each wan group contains a set of four priority queues. these queues are collectively referred to as lan queues in other portions of this document. the priority mode (802.1p, dscp, or none) for each ethernet port can be independently selected using the su.lp1c and su.lp2c registers. the dscp function is a simple en able/disable function, with all of the other parameters (ethernet frame format, and ethernet ty pe) being discovered by t he device. see section 8.16.6 for more information on programming the priority table. figure 8-15. differentiated services code point (dscp) header information ethernet byte # bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 2 3 4 5 6 destination address (da) 7 8 9 10 11 12 source address (sa) 13 ethernet type / length (msb) 14 ethernet type / length (lsb) 15 ip version ip type 16 dscp priority ect ce 17+ < ip header continues?>
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 72 of 375 8.16.6 programming the priority table the user-programmable priority tabl e is accessed indirectly through the su.ptc , su.ptaa , su.ptwd , su.ptrd , and su.ptsa registers. the device contains a single table, with the msb of the table address ( su.ptaa.ptaa ) used to distinguish the lan port in multi-port devices. when a frame is received, the pcp or dscp value in the received frame is the address used to lo ok up the user-programmed priority level in the priority table. the device does not require that the priority mapping be linear or monotonic. arbitrary assignments are allowed. note that while the dscp/pcp protocol definitions use a higher value to indi cate a higher priority, the device uses a lower value to indicate a higher priority. as an example, for the values pcp = 000b and dscp = 00000b (as defined by their protocol definitions as lowest priority) most users will choose to assign the associated priority table address location ( su.ptaa.ptaa[6:1] =000000b) a value of 11b, indicating the lowest possible priority. similarly for the values pcp = 111b and dscp = 111111b, typically t he associated priority table address will be assigned a value of 00b. example priority table configurations for a single port are shown in the tables below. table 8-12. example priority table configuration for dscp ptaa[6:1] su.ptwd/ su.ptrd ptaa[6:1] su.ptwd/ su.ptrd ptaa[6:1] su.ptwd/ su.ptrd ptaa[6:1] su.ptwd/ su.ptrd 000000 11 010000 10 100000 10 110000 01 000001 11 010001 10 100001 10 110001 01 000010 11 010010 10 100010 10 110010 01 000011 10 010011 10 100011 10 110011 01 000100 10 010100 10 100100 10 110100 01 000101 10 010101 10 100101 10 110101 01 000110 10 010110 10 100110 10 110110 01 000111 10 010111 10 100111 10 110111 01 001000 10 011000 10 101000 10 111000 01 001001 10 011001 10 101001 10 111001 01 001010 10 011010 10 101010 10 111010 01 001011 10 011011 10 101011 10 111011 01 001100 10 011100 10 101100 10 111100 01 001101 10 011101 10 101101 10 111101 01 001110 10 011110 10 101110 10 111110 01 001111 10 011111 10 101111 10 111111 00 * more guidance on priority mapping for legacy compatibility can be found in rfc 2474.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 73 of 375 table 8-13. example priority table configuration for pcp ptaa[6:1] su.ptwd/ su.ptrd 000000 11 000001 11 000010 10 000011 10 000100 01 000101 01 000110 01 000111 00
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 74 of 375 8.17 oam support with frame trapping, extraction, and insertion the device has the ability to insert and extract frames from /to the host microprocessor from both the wan interface and the lan interface. there are four user-accessible fifo s for this purpose: one for wan insertion, one for wan extraction, one for lan insertion, and one for lan extraction. each fifo has the ability to issue an interrupt when it is empty (insertion fifos) or has a frame available (ext raction fifos). in order for frames to be extracted by the host microprocessor, they must first be ?trapped?. the device has two ?traps? for capturing frames for extraction ? the lan trap and the wan trap. the maximum frame si ze that may be trapped or inserted is 2048 bytes. the lan trap (when appropriately enabled) inspects each frame received on the ethernet interface for its ethernet destination address (da), vlan tag, q- in-q tag, and ethernet type. these pa rameters help to determine what to do with each frame. the lan trap is logically located between the ethernet mac and the circuitry that performs forwarding to the wan groups. the wan trap (when appropriately enabled) inspects each fr ame received on the serial interface for its ethernet destination address (da), vlan tag, q-in-q tag, ether net type, or user-programmable header value. the wan header trap enables trapping on slarp, gfp pti/upi, gfp cid or shim tag. the wan trap is logically located after the line decoding functions (bit/byte destuffing, de scrambling), and the decapsulator packet processing circuitry. note that spi ?burst mode? is not applicable for frame in sertion or extraction, due to the indirect access of the extract and insert queues. there are 6 ethernet frame formats supported for qos and oam frame extraction. the supported frame formats are diagramed in figure 8-16 and include: ? dix ? vlan tagged dix ? q-in-q tagged dix ? 802.3 llc/snap ? vlan tagged 802.3 llc/snap ? q-in-q tagged 802.3 llc/snap the user is not required to specify or configure an ethernet frame format beca use it is normal for lan traffic to simultaneously carry multiple different ethernet formats.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 75 of 375 figure 8-16. supported trapped ethernet frame types byte # dix vlan tagged dix q-in-q tagged dix 802.3 llc/snap vlan tagged 802.3 llc/snap q-in-q tagged 802.3 llc/snap * 0 1 2 3 4 5 destination address destination address destination address destination address destination address destination address 6 7 8 9 10 11 source address source address source address source address source address source address 12 13 ethernet type length 14 15 vlan tag q-in-q tag vlan tag q-in-q tag 16 llc header (aa aa 03) 17 ethernet type length 18 19 vlan tag snap oui (00 00 00) vlan tag 20 llc header (aa aa 03) 21 ethernet type ethernet type length 22 23 snap oui (00 00 00) 24 llc header (aa aa 03) 25 ethernet type 26 27 snap oui (00 00 00) 28 29 ethernet type * ethertype trapping of this format supported by the lan trap only.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 76 of 375 8.17.1 frame trapping frames from the lan interface can be trapped by vl an id, ethernet type, broadcast address, management multicast address (01:80:c2:xx:xx:xx), de stination address, or a range of dest ination addresses. frames from the wan interface can be trapped by vlan id, ethernet type, broadcast address, management multicast address (01:80:c2:xx:xx:xx), destination addre ss, a range of destination addresses, or by a user-programmable header comparison. lan trapping is enabled in the su.lpm register. wan trapping is enabled in the su.wem register. the lan trap can only be user configured to monitor one ethernet port. the selection of lan port to be monitored is done with the su.lpm.leep bit. the wan trap can only monitor for wan extract conditions on one (of the four possible) decapsulator (wan group) data streams. the selection of the wan group to monitor is done with su.wem.weds[1:0] . the maximum frame size that may be trapped is 2kbytes. 8.17.1.1lan-vlan trapping when trapping frames received on the lan interface by vl an id, the user configures the vlan ids (vids) to be trapped using the lan-vlan table. trapping is then enabled or disabled with the su.lpm.levit bit. see section 8.16 for more information on vlan configuration. only one lan port can be allowed to forward frames to the lan extract queue (which of the two ports is determined by us er configuration). if vlan forwarding is enabled, and the 4-bit value returned from the lan-vlan table indicates ?extra ct?, but the port that the frame is associated with has not been configured to forward to the lan extract queue, then the ?extract? status retu rned from the vlan table is ignored. for more details on lan-vlan table programming, see section 8.16.2. 8.17.1.2lan ethernet type trapping when trapping frames received on the lan interface by ethernet type, the user can configure and 2-byte ethernet type field to be trapped in the su.leet register. trapping is then enabled or disabled with the su.lpm.leett bit. ethernet type trapping enables the capture of arp, bpdu, and other management traffic. 8.17.1.3lan ethernet destination address trapping when trapping frames received on the lan interface by unicast destination address, the user programs the destination address for extraction into the su.ledal , su.ledam , and su.ledah registers. by using a mask for the lower two bytes of the da in the su.ledax register, all of the addresses within a range can be forwarded to the lan extract queue. trapping is then enabled or disabled with the su.lpm.ledat bit. when trapping frames received on the lan interface by management multicast addres s (01:80:c2:xx:xx:xx), the user simply enables extraction with the su.lpm.lmgmtt bit. all trapped frames will be forwarded to the lan extract queue. when trapping frames received on the lan interface by broadcast address (ff:ff:ff: ff:ff:ff), the user simply enables extraction with the su.lpm.lbat bit. all trapped frames will be forwarded to the lan extract queue. 8.17.1.4wan ethernet destination address trapping when trapping frames received on the wan interface by un icast destination address (da), the user programs the destination address for extraction into the su.wedal , su.wedam , and su.wedah registers. by using a mask for the lower two bytes of the da in the su.wedax register, all of the management addresses within a range can be forwarded to the wan extract queue. trap ping is then enabled or disabled with the su.wem.wedat bit. when trapping frames received on the wan interface by management multicast addres s (01:80:c2:xx:xx:xx), the user simply enables extraction with the su.wem.wmgmtt bit. all trapped frames will be forwarded to the wan extract queue. when trapping frames received on the wan interface by broadcast address (ff:ff:ff:ff:ff:ff), the user simply enables extraction with the su.wem.wbat bit. all trapped frames will be forwarded to the wan extract queue.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 77 of 375 8.17.1.5wan-vlan trapping when trapping frames received on the wan interface by vlan id, the user configures the vlan ids (vids) to be trapped using the wan-vlan table. trapping is then enabled or disabled with the su.wem.wevit bit. see section 8.16 for more information on vlan configuration. on ly one wan group decapsulator can be allowed to forward frames to the wan extract queue at a time (d etermined by user configuration). if vlan trapping is enabled, and the 4-bit value returned from the wan-vlan tabl e indicates ?extract?, but the port that the frame is associated with has not been configured to forward to t he wan extract queue, then the ?extract? status returned from the wan-vlan table is ignored. for more det ails on wan-vlan table programming, see section 8.16.2. 8.17.1.6wan ethernet type trapping when trapping frames received on the wan interface by ethernet type, the user can configure and 2-byte ethernet type field to be trapped in the su.weet register. trapping is then enabled or disabled with the su.wem.weett bit. the wan ethernet type trap is valid only wi th frame formats in which the ethernet type occurs in the first 32 bytes. thus, the wan ethernet type trap is not valid with the following frame types: ? 4-byte encapsulation header with q-in-q & std vlan & llc/snap (hdlc or gfp-null) ? 8-byte encapsulation header with q-in-q & std vlan & llc/snap (hdlc or gfp-linear) ? 8-byte encapsulation header with std vlan & llc/snap (hdlc or gfp-linear) 8.17.1.7wan header trapping trapping can also be performed on any two consecutive bytes within the first 8 bytes of frames received from the wan interface. when trapping frames received on the wan interface by hea der, the user configures a 2-byte value to be trapped in the su.weht register. the offset is configured in the su.wehtp register. trapping is then enabled or disabled with the su.wem.weht bit. 8.17.2 frame extraction and frame insertion extraction of trapped frames through the microport is do ne one byte at a time, with the beginning of the frame being read first. the device must be configured to properly trap frames as described in section 8.17.1. the user may enable an interrupt to alert the host processor that a frame is available for extraction via the gl.msier3 interrupt enable register. a latched status register ( gl.mlsr3 ) may also be used as indication that a frame is available for extraction. when a trapped frame is availabl e, the user must select the correct fifo with the gl.mcr1 register. the user must then read the length of the frame from gl.msr1 or gl.msr2 in order to know how many bytes to extract. the user then reads one byte at a time from the fifo read access register ( gl.mfarr ) to extract the entire frame. when the entire frame has been read, the user indicates that the frame may be discarded from the fifo with the gl.mfawr.rd_dn bit. steps for frame extraction: 1. read the gl.msr3 lan/wan fifo extraction available status bi t to verify fifo has a frame to be read. 2. select the corresponding fifo via gl.mcr1 . 3. read the size of frame in bytes from gl.msr1 or gl.msr2 . 4. read the frame from the gl.mfarr register one byte at a time. 5. write a 0-to-1 transition to gl.mfawr.rd_dn . 6. repeat step 1. insertion of a frame through the host microport is done one byte at a time, with the beginning of the frame written first. the user must first configure the lan insertion settings and enable insertion via the su.lim register, or configure the wan insertion settings and enable insertion via the ar.mqc register. the correct fifo must then be selected with the gl.mcr1 register. the length of the frame to be inserted must then be written into gl.mcr2 or gl.mcr3 . the user proceeds to write one byte of the fr ame at a time to the fifo access register, gl.mfawr , beginning with the first byte of the frame. each write to this address automatically increments the pointer of the selected fifo. when the entire frame has been written, the gl.mfawr.wr_dn bit is used to indicate that the frame is ready for transmission. steps for frame insertion: 1. configure the lan insertion settings in the su.lim register, or wan insertion settings in ar.mqc . 2. read the gl.msr3 lan/wan queue empty status bit to verify fifo is empty.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 78 of 375 3. select the appropriate fifo for insertion via gl.mcr1 . 4. write the size of frame in bytes to gl.mcr3 for lan insertion, gl.mcr2 for wan insertion. 5. write the frame to the gl.mfawr.wpkt[0:7], one byte at a time. 6. write a 0-to-1 transition to gl.mfawr.wr_dn . 7. repeat step 1. frames loaded into the wan insertion fifo should not in clude the gfp length and chec fields. inserted frames should include all other applicable gfp/hdlc header information and a valid hecs. the header information on inserted frames may be different than the header of norm al traffic to allow for a number of management protocols to be present on the link. the only modifications made by the device to data placed in the wan insertion queue are the addition of the gfp length/chec, the line co ding functions of bit/byte stuffing, and x 43 +1 scrambling, if enabled. frames loaded into the lan insertion fifo should be co mplete and valid ieee 802.3 or dix ethernet frames. if the ethernet mac has been configured to add a fcs to all frames ( su.lim.lp1ce or su.lim.lp2ce ), the inserted frame should not contain an ethernet fcs. the frame load ed into the insertion fifo should not contain a preamble or start frame delimiter, as these will be automatically adde d by the mac. frames insert ed to the lan do not pass through a decapsulator. 8.17.2.1wan insert forwarding the wan insert queue can be user assigned to be mu ltiplexed with only one lan queue group. the group scheduler for the assigned lan queue group multiplexes the wan insert data with the data from the lan queue group. 8.17.3 oam by ethernet de stination address (da) the device can be configured to directly trap broadc ast, management multicast (01:80:c2:xx:xx:xx), and unicast frames by ethernet destination addres ses for extraction by a microprocessor. the host microprocessor can be user-programmed for parsing, interpreting, and responding to oam messages. 8.17.4 oam by ip address when a node on the network first tries to send a managem ent frame to the device, the transmitting node would normally broadcast an arp request for the unknown ip addr ess, asking for the network to resolve the ip address to a physical mac address. the device is able to trap arp request using the broadcast address trap. the user software should examine each arp request, and when appropri ate, insert a frame in response to the arp request that will associate the device's management mac address with the desired ip address. the network then transmits frames with the da value of the physical mac address in the arp response. the device would then trap the follow- on frames by mac (da) address. 8.17.5 oam by vlan tag the device can be configured to trap frames with any number of user-programmed vlan ids in the vlan table. the vlan table is accessed indirectly through the su.vtc , su.vtaa , and su.vtwd registers. the su.vtwd.lvdw bit is used to indicate a vlan id (vid) value is to be extracted if received on the lan interface. the su.vtwd.wvqfw bit is used to indicate a vlan id (vid) value is to be extracted if received on the wan interface. note that vlan trapping must also be enabled with the su.wem or su.lpm registers. 8.17.6 snmp support the device can be configured to trap unicast frames for ex traction by the microprocessor. the host microprocessor can be user-programmed for parsing, interpreting, and responding to snmp messages. hardware counters are provided for supporting portions of rfc2819 (rmo n), and portions of rfc1213 (mib-ii). see section 8.19.2 for more information on the mac management counters used for this purpose.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 79 of 375 8.18 bridging and filtering the automatic learning and filtering functions for et hernet bridging are only applicable in 10/100mbps ethernet applications. the static da filtering functions availabl e in the mac may be used for 1000mbps applications as described in section 8.19.3. the high-level features of the automatic learning and filtering functions are shown below: ? supports up to two 10/100 ethernet ports ? self-learning filtering table is ?shared? betw een the two lan ports (not 2 independent tables) ? supports a continuous stream of 64-byte frames on both ports ? automatically learns up to 4096 mac addresses ? provides automatic address aging when enabled, the automatic bridge filter monitors the la n input data stream to build a bridge filter table based on ethernet source addresses (sa). a sa learning function allows the device build a table of source addresses and their associated interface. if the sa of a received fram e is not found in the table, then the current sa is stored in the bridge filter table. the bridge filter table is then used to determine whether to forward or drop each frame as it is received. if the destination ad dress (da) of a received frame from th e lan is equal to the value of an sa that is already stored in the bridge filter table, the fr ame is discarded. if no match is found, then the frame is forwarded to the wan groups. an aging function is used to determine when a sa entry has age d to the point that it is no longer useful. the user configures an aging period in su.bfc.bfap[1-9] that defines how long an sa will be stored in the bridge table. after that time period, the entry is removed so that t he position may used by another sa value. the aging period can be user configured to any value from 1 second to 300 seconds in 1 second steps (300 seconds is the default setting). on devices with two ethernet ports, one bridge filter tabl e is shared by the 2 lan ports. an sa address that is learned on lan port 1 is treated as though it was also lear ned on lan port 2. this has the effect that each frame da received on lan port 1 is tested against all sas lear ned on lan port 1 and lan port 2 (the same is true for frame das received on lan port 2). if a da matches a stored sa from either port, the frame will be discarded. if the lan trap determines that a frame matches one of the lan extract trap co nditions, the frame is forwarded to the lan extract queue, regardless of whether the bridge filter indicate s that frame is to be discarded. 8.18.1 bridge filter table reset the bridge filter table reset function is used to clear all of the bridge table entries. this function is automatically triggered at power-up and can be manua lly triggered by the user by setting su.bfc.bftr to 1. during the bridge filter table reset operation, traffic w ill be processed as normal. the user has the option of disabling the lan ports so that there is no traffic during the bridge filter table reset process or allowing traffic to continue flowing at the same time as the bridge filter table reset process. if t he user does not disable traffic, then the table may learn some new entries before the complete table has been reset. the bridge filter table reset function takes approximately 64 ms to complete.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 80 of 375 8.19 ethernet mac indirect addressing is required to access the ether net mac registers. writing to the ethernet mac registers requires address and data information to be loaded into multip le registers, and the write operation initiated through a control bit. reading from the mac regi sters requires address information to be loaded into two registers, the read operation initiated through a control bit. after the read oper ation completes, data is r ead from four registers. algorithm for indirect mac write operation: 1) read su.mac1rwc.mcs and verify that a read/write access is not in progress. 2) write the address for the access into the su.mac1awl and su.mac1awh registers. 3) write the data to be written into the su.mac1wd0-3 registers. 4) write su.mac1rwc = 0x01. 5) poll su.mac1rwc.mcs until the bit is clear, indicating that the write operation has completed. algorithm for indirect mac read operation: 1) read su.mac1rwc.mcs and verify that a read/write access is not in progress. 2) write the address for the access into the su.mac1radh and su.mac1radl registers. 3) write su.mac1rwc = 0x03. 4) poll su.mac1rwc.mcs until the bit is clear, indicating that the read operation has completed. 5) read the data from su.mac1rd0 - su.mac1rd3 . note that only one operation can be initiated (read or write) at one time. data cannot be written or read from the mac registers until the su.mac1rwc.mcs bit has been cleared by the device. the mac registers are listed in the following table.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 81 of 375 table 8-14. mac control registers indirect address register register description 0000h su.maccr mac control register 0004h su.macffr mac frame filter register 0008h su.machthr mac hash table high register 000ch su.machtlr mac hash table low register 0010h su.gmiia mac mdio management address register 0014h su.gmiid mac mdio management data register 0018h su.macfcr mac flow control register 001ch su.vlantr mac vlan tag register 0040h su.addr0h mac filter address 0 high 0044h su.addr0l mac filter address 0 low 0048h su.addr1h mac filter address 1 high 004ch su.addr1l mac filter address 1 low 0050h su.addr2h mac filter address 2 high 0054h su.addr2l mac filter address 2 low 0058h su.addr3h mac filter address 3 high 005ch su.addr3l mac filter address 3 low 0060h su.addr4h mac filter address 4 high 0064h su.addr4l mac filter address 4 low 0068h su.addr5h mac filter address 5 high 006ch su.addr5l mac filter address 5 low 0070h su.addr6h mac filter address 6 high 0074h su.addr6l mac filter address 6 low 0078h su.addr7h mac filter address 7 high 007ch su.addr7l mac filter address 7 low 0080h su.addr8h mac filter address 8 high 0084h su.addr8l mac filter address 8 low 0088h su.addr9h mac filter address 9 high 008ch su.addr9l mac filter address 9 low 0090h su.addr10h mac filter address 10 high 0094h su.addr10l mac filter address 10 low 0098h su.addr11h mac filter address 11 high 009ch su.addr11l mac filter address 11 low 00a0h su.addr12h mac filter address 12 high 00a4h su.addr12l mac filter address 12 low 00a8h su.addr13h mac filter address 13 high 00ach su.addr13l mac filter address 13 low 00b0h su.addr14h mac filter address 14 high 00b4h su.addr14l mac filter address 14 low 00b8h su.addr15h mac filter address 15 high 00bch su.addr15l mac filter address 15 low 00c0h su.pcscr mac pcs (connection) control register 1018h su.macmcr mac miscellaneous control register table 8-15. mac status registers indirect address register register description 00c4h su.ansr mac auto-negotiation status register 00d8h su.lsr mac mii/rmii/gmii status register
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 82 of 375 table 8-16. mac counter registers indirect address register register description 0100h su.mmcctrl mac management counter control register 0104h su.mmcrsr mac management counter receive status register 0108h su.mmctsr mac management counter transmit status register 010ch su.mmcrim mac management counter receive interrupt mask 0110h su.mmctim mac management counter transmit interrupt mask 0114h su.txbc mac mmc transmit byte counter 0118h su.txfc mac mmc transmit frame counter 011ch su.txgbfc transmit good broadcast frames counter 0120h su.txgmfc transmit good multicast frames counter 0124h su.tx0_64 transmit 0-64 byte frame counter 0128h su.tx65_127 transmit 65-127 byte frames counter 012ch su.tx128_255 transmit 128-255 byte frame counter 0130h su.tx256_511 transmit 256-511 byte frames counter 0134h su.tx512_1k transmit 512-1023 byte frame counter 0138h su.tx1k_max transmit 1024-max byte frames counter 013ch su.txucast transmit unicast frame counter 0140h su.txmfc transmit multicast frames counter 0144h su.txbfc transmit broadcast frame counter 0148h su.txufe transmit underflow frames counter 014ch su.txsnglcl transmit single collision frame counter 0150h su.txmlticl transmit multiple collision frames counter 0154h su.txdfrd transmit deferred frame counter 0158h su.txltcl transmit late collision frames counter 015ch su.txxcsvcl transmit excessive collision counter 0160h su.txcrerr transmit carrier error counter 0164h su.txgbc transmit good byte counter 0168h su.txgfc transmit good frame counter 016ch su.txxcsvdf transmit excessive deferral counter 0170h su.txpause transmit pause frame counter 0174h su.txvlanf transmit vlan frame counter 0180h su.rxfc receive frame counter 0184h su.rxbc receive byte counter 0188h su.rxgbc receive good byte counter 018ch su.rxgbfc receive good broadcast frame counter 0190h su.rxmfc receive multicast frame counter 0194h su.rxcrc receive crc error counter 0198h su.rxalgn receive alignment error counter 019ch su.rxrunt receive runt error counter 01a0h su.rxjbbr receive jabber error counter 01a4h su.rxundrsz receive undersize frame counter 01a8h su.rxovrsz receive oversize frame counter 01ach su.rx0_64 receive 0-64 byte frame counter 01b0h su.rx65_127 receive 65-127 byte frame counter 01b4h su.rx128_255 receive 128-255 byte frame counter 01b8h su.rx256_511 receive 256-511 byte frame counter 01bch su.rx512_1k receive 512-1023 byte frame counter 01c0h su.rx1k_max receive 1024-max byte frame counter 01c4h su.rxufc receive unicast frame counter 01c8h su.rxlnerr receive length error counter 01cch su.rxrange receive out of range counter 01d0h su.rxpause receive pause frame counter 01d4h su.rxovfl receive overflow counter 01d8h su.rxvlan receive vlan frame counter 01dch su.rxwdog receive watchdog error counter
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 83 of 375 8.19.1 phy mii management block and mdio interface the mii management block allows for the host to control up to 32 phys, each with 32 registers. the mii block communicates with the external phy using 2-wire serial interface composed of mdc (serial clock) and mdio for data. the mdio data is valid on the rising edge of t he mdc clock. the frame format for the mii management interface is shown figure 8-17. the read/write control of the mii management is accomplished through the indirect su.gmiia mii management address register and da ta is passed through the indirect su.gmiid data register. these indirect registers are accessed thro ugh the mac control registers defined in table 8-14. the mdc clock is internally generated and runs at 1.67mhz. note that the device provides a single mii management port, and all control registers for this function are located in mac 1. figure 8-17. mii management frame read 111...111 01 01 10 01 phya[4:0] phyr[4:0] zz 10 zzzzzzzzz z z preamble start opco de phy adrs phy reg turn aroun d data 111...111 phya[4:0] phyr[4:0] phyd[15:0] 32 bits 2 bits 2 bits 5 bits 5 bits 2 bits 16 bits idle 1 bit write
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 84 of 375 8.19.2 ethernet mac management counters for rfc2819 rmon rfc2819 rmon etherstatsentry support variabe name type support etherstatsindex integer32 user-defined by port etherstatsdatasource object identifier user-defined etherstatsdropevents counter32 su.rxovfl + su.txufe etherstatsoctets counter32 su.rxbc etherstatspkts counter32 su.rxfc etherstatsbroadcastpkts counter32 su.rxgbfc etherstatsmulticastpkts counter32 su.rxmfc etherstatscrcalignerrors counter32 su.rxcrc + su.rxalgn etherstatsundersizepkts counter32 su.rxundrsz etherstatsoversizepkts counter32 su.rxovrsz etherstatsfragments counter32 su.rxrunt etherstatsjabbers counter32 su.rxjbbr etherstatscollisions counter32 su.txltcl + ( su.txxcsvcl *16) + su.txsnglcl + ( su.txmlticl *2) etherstatspkts64octets counter32 su.rx0_64 etherstatspkts65to127octets counter32 su.rx65_127 etherstatspkts128to255octets counter32 su.rx128_255 etherstatspkts256to511octets counter32 su.rx256_511 etherstatspkts512to1023octets counter32 su.rx512_1k etherstatspkts1024to1518octets counter32 su.rx1k_max etherstatsowner ownerstring user-defined etherstatsstatus entrystatus user-defined note that implementations of the snmp rmon mib must also implement the system group of mib-ii and the if- mib.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 85 of 375 8.19.3 programmable ethernet de stination address filtering in addition to the automatic learning and f iltering features described in section 8.18, the ethernet mac has the capability to filter frames by mac dest ination address. this feat ure is available at all data rates. the user may program up to 16 destination addresses that may be allowed or disallowed. the following pseudo code is an example enabling static mac address filter 0 to allow frames with a da of 12:34:56:78:9a:bc to pass. perform an indirect write to maccr for a basic configuration: 0x004a = 0x00 ; point to maccr 0x004b = 0x00 0x0046 = 0x0c 0x0047 = 0x88 0x0048 = 0x00 0x0049 = 0x00 0x004c = 0x01 ; issue write command configure mac filter #0 to a value of 12:34:56:78:9a:bc and enable it: 0x004a = 0x40 ; point to addr0h 0x004b = 0x00 0x0046 = 0x9a ; note the byte order of 9a:bc. 0x0047 = 0xbc 0x0048 = 0x00 0x0049 = 0x80 0x004c = 0x01 ; issue write command 0x004a = 0x44 ; point to addr0l 0x004b = 0x00 0x0046 = 0x12 ; note the byte order of 12:34:56:78 0x0047 = 0x34 0x0048 = 0x56 0x0049 = 0x78 0x004c = 0x01 ; issue write command configure the mac filtering in macfcr: 0x004a = 0x04 ; point to macfcr 0x004b = 0x00 0x0046 = 0x00 ; 0x01 will disable filtering 0x0047 = 0x00 0x0048 = 0x00 0x0049 = 0x00 ; 0x80 will disable filtering 0x004c = 0x01 ; issue write command
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 86 of 375 8.20 ethernet frame encapsulation the figure below depicts the layer 1 mapping and laye r 2 protocol encapsulation options available: 8.20.1 transmit packet pr ocessor (encapsulator) the data from each wan group is processed by the tr ansmit packet processor (or encapsulator) before being transmitted on the serial interfaces. the encapsulator performs bit reordering, fcs processing, frame error insertion, stuffing, frame abort sequence insertion, inte r-frame padding, vlan tag inse rtion, mpls tag insertion, ppp headers, laps headers, octet remo val, and frame scrambling. each wan group?s encaps ulation settings can be independently configured with the pp.emcr(1-4) registers. the encapsulator automatically inse rts the inter-frame fill and flag char acters based on the selection of hdlc/chdlc/laps or gfp in pp.emcr.eprtsel . a line header insertion function (in pp.elhhr and pp.elhlr ) allows the user to insert address, control, and protocol bytes for hdlc/chdlc/x.86, or type and thec bytes for gfp. the tag 1 insertion function (in pp.et1dhr and pp.et1dlr ) allows the user to insert a 4- byte mpls tag immediately before the destinati on address (da). the tag 2 insertion function (in pp.et2dhr and pp.et2dlr ) allows the user to insert a 4-byte vlan tag imme diately after the source address (sa). any existing vlan tags are ?pushed? lower in the frame. hdlc processing can be disabled. dis abling hdlc processing disables fcs processing, frame error insertion, stuffing, frame abort sequence insertio n, and inter-frame fill/padding. only bi t reordering and frame scrambling are not disabled. bit reordering changes the bit order of each byte. if bi t reordering is disabled, the outgoing 8-bit data stream dt[1:8] with dt[1] being the msb and dt[8] being the lsb is output from the transmit fifo with the msb in tfd[7] (or 15, 23, or 31) and the lsb in tfd[0] (or 8, 16, or 24) of the transmit fifo data tfd[7:0] 15:8, 23:16, or 31:24). if bit reordering is enabled, the outgoing 8-bit data str eam dt[1:8] is output from the transmit fifo with the msb in tfd[0] and the lsb in tfd[7] of the transmit fifo data tfd[7:0]. in bit synchronous mode, dt [1] is the first bit transmitted. bit reordering is configured using the pp.emcr.tbre bit. note that bit reordering is not available in the a1 device revision ( gl.idr.revn=000). fcs processing, when enabled in pp.emcr(1-4) , appends a calculated fcs to the frame. the polynomial used for fcs-16 is x 16 + x 12 + x 5 + 1. the polynomial used for fcs-32 is x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1. the fcs is inverted after calculation. if packet processing is dis abled, fcs processing is not performed. frame error insertion inserts errors into the gfp pli, dat a unit, or fcs bytes. a single bit is corrupted in each errored frame. the location of the corrupted bit is us er-programmable. error inse rtion is controlled by the pp.eeir register. gfp-f vcat laps chdlc mac ieee 802.1d bridge 802.3 synchronous links mpls / vlan tagging wan (pdh interfaces) lan side traffic mgmt hdlc
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 87 of 375 in hdlc/chdlc/laps(x.86) mode, the inter-frame fill is se lectable per wan group with pp.emcr.eiis . if packet processing is disabled, inter-frame padding is not performed. the frame scrambler is a x 43 + 1 scrambler that scrambles the entire frame data stream. frame scrambling is selectable per wan group with pp.emcr.ecfcrd . to optimize wan bandwidth in point-t o-point applications, the ethernet header information may be removed from the datagram prior to encapsulation. the encapsulator can be configured to remove either 14 or 18 bytes from each incoming frame using the pp.emcr.ere[1:0] bits. byte removal starts with the da field. removing 14 bytes will remove the da, sa, and length/type fields. remo ving 18 bytes will remove the da, sa, length/type, and vlan tag fields. once all packet processing has been completed, the serial data stream is forwarded. note that some devices in the product family have less than four encapsulators. the ds33x11 contains only encapsulator #1. the ds33w41 and ds33x42 contain only encapsulators #1 and #3. 8.20.2 receive packet processor (decapsulator) the receive packet processor accepts data from the receiv e serial interface performs frame descrambling, frame delineation, inter-frame fill filtering, frame abort detection, destuffing, frame size checking, fcs error monitoring, fcs byte extraction, and bit reordering. frame delineati on determines the frame boundar y by identifying a frame start or end flag. receive packet processing can be di sabled. disabling packet processing disables frame delineation, inter-frame fill filtering, frame abort detection, destuffing, frame size checking, fcs error monitoring, and fcs byte extraction. only frame descrambling and bit re ordering are not disabled. the frame descrambler is a self-synchronizing x 43 + 1 descrambler. inter-frame fill filtering removes the inter-frame fill be tween frames. when a frame end flag is detected, all data is discarded until a frame start flag is detected. the inter-fra me fill can be flags or all 1s. the number of 1s between flags does not need to be an integer number of bytes, and if at least seven 1s are detected in the first 16 bits after a flag, all data after the flag is discarded until a start flag is detected. frame abort detection searches for a frame abort sequence between the frame start flag and a frame end flag, if an abort sequence is detected, the frame is marked with an abort indication, the aborted frame count is incremented, and all subsequent data is discarded until a valid frame start flag is detected. destuffing removes the extra data inserted to prevent dat a from mimicking a hdlc/chdlc/x.86 flag or an abort sequence. a start flag is detected, destuffing is performe d until an end flag is detected. the start and end flags are discarded. in bit synchronous mode, bit destuffing is perfo rmed. bit destuffing consists of discarding any '0' that directly follows five contiguous 1s. after destuffing is completed, the serial bit stream is forwarded. frame size validation checks each frame for a programmable maximum size. as the frame data comes in, the total number of bytes is counted. if the frame length is below the minimum size limit, the frame is marked with an aborted indication, and the frame size violation count is incremented. if the frame length is above the maximum size limit, the frame is marked with an aborted indication, the frame size violation count is incremented, and all frame data is discarded until a frame start is received. the minimum and maximum lengths include the fcs bytes, and are determined after destuffing has occurred. fcs error monitoring checks the fcs and aborts error ed frames. if an fcs error is detected, the fcs errored frame count is incremented and the frame is marked with an aborted indication. if an fcs error is not detected, the receive frame count is incremented. the fcs type (16-bit or 32-bit) is programmable. fcs byte extraction discards the fc s bytes. if fcs extraction is enabled, t he fcs bytes are extracted from the frame and discarded. if fcs extraction is disabled, the fcs by tes are stored in the receive fifo with the frame. bit reordering changes the bit order of each byte. normally, the first bit of each byte in the received data stream is assumed to be the msb. if bit reordering is enabled, the firs t bit of each byte in is assumed to be the lsb. once all of the packet processing has been comp leted, the data stream is passed to the wan queues. bit reordering is configured using the pp.dmcr.rbre bit. note that bit reordering is not available in the a1 device revision ( gl.idr.revn=000). the decapsulator collects 2 statistics; the number of good frames and number of errored frames due any errors. these statistics are latched bit counters and are cleared when read by the user. the decapsulator must be configured to remove the 4-by te encapsulation line header information if it is present. the 4-byte removal function is selected using the pp.dmcr.dr1e control bit. when enabled, 4 bytes are removed
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 88 of 375 immediately after the chec bytes when in gfp mode or afte r the start flag when in hdlc mode. this bit should be set to 1 for x.86, chdlc and gfp transport. this bit sh ould be equal to 0 for hdlc traffic with no headers. the decapsulator can be configured to remove a mp ls tag prior to forwarding to the lan interface. the 4-byte removal function used for this purpose is enabled using the pp.dmcr.dr2e control bit. when enabled, 4 bytes are removed after the first remove (dr1e) function. note that pp.dmcr.dr1e must be properly configured for this function to operate correctly. the decapsulator can be configured to remove a vl an tag prior to forwarding to the lan interface. the 4-byte removal function used for this purpose is enabled using the pp.dmcr.dr3e control bit. when enabled, 12 bytes are skipped (ethernet da/sa) and the following 4 bytes are removed. this function is performed after the decapsulator remove function 1 and/or decapsulator remove function 2 have been performed. when decapsulator remove functions 1 and 2 are disabled, 12 bytes are skipped from the beginning of the ethernet frame. to optimize wan bandwidth in point-to-point applicati ons, ethernet header information may be removed from the datagram during wan transport. the decapsulator can be configured to replace the missing ethernet header information prior to forwarding to the lan interface, by in serting a 14 or 18 byte values to each incoming frame. this function is enabled using the pp.dmcr.dae[1:0] control bits. when enabled, a 14-byte value from the pp.da1dr through pp.da7dr registers or a 18-byte value from the pp.da1dr through pp.da9dr registers will be inserted after the chec bytes in gfp mode, or afte r the hdlc header/flag when in hdlc mode. once all packet processing is performed by the decapsulator, the ethernet frames are forwarded to the mac for transmission on the lan interface. note that some devices in the product family have less than four decapsulators. the ds33x11 contains only decapsulator #1. the ds33w41 and ds33x 42 contain only decapsulators #1 and #3.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 89 of 375 8.20.3 gfp-f encapsul ation and decapsulation the gfp-f protocol provides a method for encapsulating et hernet frames over point-to -point serial links. the device expects a frame or multiframe sy nchronization signal to provide the byte boundary. this is provided by the rsync and tsync pins. the receive functional timing is shown figure 11-13 . the transmit functional timing is shown in figure 11-9 . gfp-f encapsulation is selected with the eprtsel regist er bit. however, there are two types of gfp-f: null and linear extension mode. the device allows the selection of gfp linear extension through a user-configured ?gfp crc mode? bit for each encaps ulator and decapsulator ( pp.emcr.egcm and pp.dmcr.dgcm ). for each mode, several additional register settings are required as outlined in the following sections. in both gfp modes, the line header insertion function (in pp.elhhr and pp.elhlr ) must be programmed by the user to insert the required gfp type and thec fields . this structure, which is also known as the gfp payload header, indicates the contents of the en capsulated payload. the type field consis ts of sub fields that are used to indicate the payload type (pti), payload fcs indicator (pfi) extension header identifier (exi) and user payload identifier (upi). table 8-17. gfp type/thec field (payload header) definition bit # frame byte number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 & 6 pti pfi exi upi 7 & 8 15 thec thec 0 the pti field will normally be programmed to 000b for su bscriber traffic. a pti of 100b may be used for management traffic in some applications. the pfi bit should match the user configured setting for pfcs in pp.dmcr . dfcsad and pp.emcr.efcsad . a pfi value of 1 indicates that the payload includes a pfcs. the exi bits should equal 0000b for gfp null, and 0001b for gfp linear extension. the upi field should be configured to match the type of traffic being transported. po ssible upi values are shown in the table below. table 8-18. gfp upi definitions upi bits <7:0> gfp payload information 0000 0001 frame-mapped ethernet 0000 0010 frame-mapped ppp 0000 1000 frame-mapped multiple access protocol over sdh (mapos) 0000 1101 frame-mapped mpls (unicast) 0000 1110 frame-mapped mpls (multicast) 0000 1111 frame-mapped is-is 0001 0000 frame-mapped ipv4 0001 0001 frame-mapped ipv6 1111 0000 through 1111 1110 reserved for proprietary use
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 90 of 375 the final two bytes of the type/thec field are used to perform header validation. the thec calculation is a crc- 16 operation in which the two byte pli is multiplied by x 16 and divided (modulo 2) by the polynomial x 16 +x 12 +x 5 +1. another common representation for this polynomial is 0x1021. the initialization value for the operation is 0x0000. the msb of the pli is bit 16, and the resulting remainde r of the operation is the thec. to avoid requiring this algorithm implementation in the user?s software, so me common type and the corresponding thec values are provided in the table below. table 8-19. example gfp type + thec values configuration gfp type (hex) thec (hex) client data, includes pfcs, gfp null, ethernet 1001 1352 client data, no pfcs, gfp null, ethernet 0001 1021 client data, includes pfcs, gfp linear, ethernet 1101 2063 client data, no pfcs, gfp linear, ethernet 0101 2310 management data, includes pfcs, gfp null, ethernet 9001 08ca management data, no pfcs, gfp null, ethernet 8001 0bb9 management data, includes pfcs, gfp linear, ethernet 9101 3bfb management data, no pfcs, gfp linear, ethernet 8101 3888 when receiving either gfp null or gfp linear extension frames from the wan, the pp.dmcr.dr1e bit should be set to 1 in order to remove the incoming gfp type and thec bytes from the data stream. the itu-t g.8040 specification requires that when using gf p over a pdh link, the vcat byte position must not be used for payload information. the reservation or usag e of the vcat byte position is selected via the vcat.tcr3.tnvcgc bit.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 91 of 375 8.20.3.1gfp-f null when configured for gfp null operation, no additional h eader information is required. the encapsulator?s tag 1 insertion function (in pp.et1dhr and pp.et1dlr ) is available to insert a 4-byte mpls tag immediately before the ethernet destination address (da), and the tag 2 insertion function (in pp.et2dhr and pp.et2dlr ) is available to insert a 4-byte vlan tag immediately after the source address (sa). any existing vlan tags are ?pushed? lower in the frame. the resulting encapsulated frame format is shown below. note that when enabled in this mode, the pfcs calculation begins with the 9 th byte of the frame. figure 8-18. gfp-f null encapsulated frame format gfp chec 1st octet of gfp type 2nd octet of gfp type 1st octet of gfp thec 2nd octet of gfp thec destination address (da) source address (sa) length / ethertype bytes 2 1 1 1 1 6 6 4 mac client data 46-1500 pad (optional) fcs for mac 4 gfp payload fcs (optional) 4 msb lsb q-in-q vlan tag (existing/optional) vlan tag (optional) 4 2 gfp payload length (pli) 2
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 92 of 375 8.20.3.2gfp-f linear extension when configured for gfp linear extension mode, an additional header is required. the encapsultor?s tag 1 insertion function (in pp.et1dhr and pp.et1dlr , enabled with pp.emcr.et1e ) is used to insert the 4-byte gfp extension header value. if receiving gfp linear extension frames from the wan, the pp.dmcr.dr2e bit should be set to 1 in order to remove the incoming gfp cid, spare, and ehec bytes from the data stream. table 8-20. gfp cid/spare/ehec (extension header) field definition bit # frame byte number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 & 10 cid spare 11 & 12 15 ehec ehec 0 the final two bytes of the linear extension header fi eld are used to perform header validation. the ehec calculation is a crc-16 operation in which the two byte cid (and spare) value is multiplied by x 16 and divided (modulo 2) by the polynomial x 16 +x 12 +x 5 +1. another common representation for this polynomial is 0x1021. the initialization value for the operation is 0x0000. the msb of the cid is bit 16, and the resulting remainder of the operation is the ehec. to avoid requiring this algorithm implementation in the user?s software, several example cid + spare values and the corresponding ehec values are provided in the table below. table 8-21. example cid + spare + ehec values cid + spare (hex) ehec (hex) 0000 0000 0100 3331 0200 6662 0400 ccc4 0800 89a9 1000 0373 2000 06e6 4000 0dcc 8000 1b98 ff00 03ff
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 93 of 375 the encapsulator?s tag 2 insertion function (in pp.et2dhr and pp.et2dlr ) is available to insert a 4-byte vlan tag immediately after the source address (sa). any exis ting vlan tags are ?pushed? lower in the frame. the resulting encapsulated frame format is shown below. note that when in this mode, the pfcs calculation begins with the 13 th byte of the frame. the received ehec value is veri fied by the decapsulator. while in linear mode, if the ehec verification fails, the received wan packet is discarded. figure 8-19. gfp-f linear extension encapsulated frame format gfp chec 1st octet of gfp type 2nd octet of gfp type 1st octet of gfp thec 2nd octet of gfp thec destination address (da) source address (sa) length / ethertype bytes 2 1 1 1 1 6 6 4 mac client data 46-1500 pad (optional) fcs for mac 4 gfp payload fcs (optional) 4 msb lsb q-in-q vlan tag (existing/optional) vlan tag (optional) gfp cid, spare, & ehec 4 2 4 gfp payload length (pli) 2
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 94 of 375 8.20.4 x.86 e ncoding and decoding x.86 protocol provides a method for encapsulating ethernet frame for eventual transport on a sonet or sdh network. laps provides a byte-synchronou s hdlc-like framing structure for en capsulation of ethernet frames, but is not as susceptible to dynamic bandwidth expansi on as bit-stuffed hdlc. laps encapsulated frames can be used to send data onto a sonet/sdh network. the device expects a byte synchronization signal to provide the byte boundary for the x.86 receiver. this is provided by the rsync pin. the functional timing is shown figure 11-13. the x.86 transmitter provides a byte boundary indica tor with the signal tsync. the functional timing is shown in figure 11-9. a line header insertion function (in pp.elhhr and pp.elhlr ) allows the user to inse rt address, control, and sapi bytes. the tag 1 in sertion function (in pp.et1dhr and pp.et1dlr ) allows the user to insert a 4-byte mpls tag immediately before the destination addr ess (da). the tag 2 insertion function (in pp.et2dhr and pp.et2dlr ) allows the user to insert a 4-byte vlan tag imme diately after the source address (sa). any existing vlan tags are ?pushed? lower in the frame. figure 8-20. laps / x.86 en capsulated frame format flag(0x7e) address(0x04) control(0x03) 1st octet of sapi(0xfe) 2nd octet of sapi(0x01) destination address (da) source address (sa) length / ethertype bytes 1 1 1 1 1 6 6 4 mac client data 46-1500 pad (optional) fcs for mac 4 fcs for laps flag(0x7e) 4 msb lsb q-in-q vlan tag (existing/optional) vlan tag (optional) mpls tag (optional) 4 2 1 4
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 95 of 375 the device will encode the mac frame with x.86 / laps encap sulation on a complete seri al stream if configured for x.86 mode in the register pp.emcr . the device provides the following functions: ? 32 bit fcs ? x 43 +1 scrambling/descrambling ? transparency processing ? rate adaptation removal. received frames are aborted if: ? if 7d,7e is detected. this is an abort frame sequence in x.86 ? invalid fcs is detected ? the received frame has less than 6 octets ? control, sapi and address field are mism atched to the programmed value ? octet 7d and octet other than 5d,5e,7e or dd is detected when in x.86 mode, the device encapsul ates frames with a start flag (7eh), address, contro l and sapi field, followed by the frame and a 32-bit fcs. a x 43 +1 scrambler scrambles the data. between the start and stop flags, data bytes matching the start/abort flag is replaced with a 2-byte escape sequence. figure 8-20 shows a frame encapsulated in a laps frame. options for mpls and vlan and q-in-q inform ation bytes are user configured. in the receive direction, rate adaptation octe ts are removed. in the transmit direct ion, idle code fill is used, and rate adaptation is not performed. the encapsul ator performs transparency processi ng or octet stuffing to ensure that the data does not mimic flags. for transparency processing, 7eh is translated to 7d 5eh and 7dh is translated to 7d 5dh. byte stuffing consists of detecting bytes t hat mimic flag and escape sequence bytes (7eh and 7dh), and replacing the mimic bytes with an escape sequence (7dh ) followed by the mimic byte exclusive 'or'ed with 20h.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 96 of 375 8.20.5 hdlc e ncoding and decoding the hdlc protocol provides a simple method for encapsul ating ethernet frames over point-to-point serial links. hdlc encapsulation can be bit or byte synchronous. in byte synchronous mode, byte stuffing is performed. byte stuffing consists of detecting bytes that mimic flag and escape sequence bytes (7eh and 7dh), and replacing them with an escape sequence (7dh) followed by the byte ?e xclusive-or?ed? with 20h. in bit synchronous hdlc, 5 consecutive ones must always be followed by a 0 to av oid mimicking a start or stop flag. note that the 5 consecutive ones can straddle any 2 co nsecutive bytes. hdlc frame encaps ulation of the frame is shown in figure 8-21. a line header insertion function (in pp.elhhr and pp.elhlr ) allows the user to inse rt address, control, and protocol bytes. the tag 1 insertion function (in pp.et1dhr and pp.et1dlr ) allows the user to insert a 4-byte mpls tag immediately before the destination ad dress (da). the tag 2 insertion function (in pp.et2dhr and pp.et2dlr ) allows the user to insert a 4-byte vlan tag imme diately after the source address (sa). any existing vlan tags are ?pushed? lower in the frame. the device provides the foll owing hdlc functions. ? insertion of hdlc flags ? performs hdlc bit and byte stuffing ? insertion of payload fcs (32 bit / 16 bit) ? selectable x 43 +1 scrambling ? selectable idle: all ones or flag insertion hdlc receive compatibility: ? hdlc with no line headers and encapsulated ethernet frames. ? hdlc with laps headers. ? hdlc with cisco hdlc headers. ? hdlc encapsulated ethernet frames with vlan tags . ? hdlc encapsulated ethernet frames with mpls headers. ? bit or byte synchronous stuffed hdlc ? hdlc fcs lengths of 0, 16, or 32 bits. ? interframe fill can be 7eh or all 1s. ? x 43 +1 scrambled frame.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 97 of 375 figure 8-21. hdcl encapsulated frame format flag(0x7e) address (optional) control (optional) 1st octet of protocol (optional) 2nd octet of protocol (optional) destination address (da) source address (sa) length / ethertype bytes 1 1 1 1 1 6 6 4 mac client data 46-1500 pad (optional) fcs for mac 4 fcs (optional) flag(0x7e) 0 / 2 / 4 msb lsb q-in-q vlan tag (existing/optional) vlan tag (optional) mpls tag (optional) 4 2 1 4
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 98 of 375 8.20.6 chdlc e ncoding and decoding the chdlc protocol provides a simple method for encapsul ating ethernet frames over point-to-point serial links. a line header insertion function (in pp.elhhr and pp.elhlr ) allows the user to inse rt address, control, and protocol bytes. the tag 1 insertion function (in pp.et1dhr and pp.et1dlr ) allows the user to insert a 4-byte mpls tag immediately before the destination ad dress (da). the tag 2 insertion function (in pp.et2dhr and pp.et2dlr ) allows the user to insert a 4-byte vlan tag imme diately after the source address (sa). any existing vlan tags are ?pushed? lower in the frame. figure 8-22. chdlc encapsulated frame format flag(0x7e) address (0x0f) control (0x00) 1st octet of protocol 2nd octet of protocol destination address (da) source address (sa) length / ethertype bytes 1 1 1 1 1 6 6 4 mac client data 46-1500 pad (optional) fcs for mac 4 fcs (optional) flag(0x7e) 0 / 2 / 4 msb lsb q-in-q vlan tag (existing/optional) vlan tag (optional) mpls tag (optional) 4 2 1 4
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 99 of 375 8.21 cir/cbs controller the device provides a committed information rate (cir) / committed burst rate (cbs) provisioning facility. the cir/cbs can be used to restrict the tran sport of received mac data to a specific rate. the cir will restrict the data flow from the receive mac to transmit packet proc essor. policing parameter s are user-defined in the su.l1pp and su.l2pp registers. the data rate increments for cir/cbs prov ision that are available to the user are based on the operational data rate and are approximately: 64kbps from dc to 2mbps, 2mbps from 2mbps to 64mbps, and 16mbps from 16mbps to 416mbps. the cir function is bas ed on a time-averaged value of bytes transmitted. when the cir is enabled, the average bytes per second of ether net traffic forwarded to the serial wan interfaces is limited to the configured cir. the transmit cbs for all cir settings is select able using su.l1pp.cbss and su.l2pp.cbss. some details regarding operati on of the cir are as follows: ? the maximum value of cir cannot effectively ex ceed the aggregate serial transmit line rate. ? if the data rate received from the ethernet interface is higher than the cir, the device can be configured to invoke flow control or to discard frames to reduce the forwarded traffic rate. ? cir function is only available for data received at t he ethernet interface to be forwarded to wan. there is not a cir function for data arriving from the wan to be sent to the ethernet interface. the user provides the followi ng configuration parameters: parameter configured settings description off enables/disables the cir/cbs policing function. policing pause enabled enables pause fl ow control when cir is exceeded. policing policing discard enabled enabled discarding of frames when cir is exceeded. 64kbps to 2mbps low-range cir. 2mbps to 64mbps mid-range cir. operating range 16mbps to 416mbps high-range cir. cir credit threshold 8-bit value this setting allows approxima te incremental steps of: 64kbps each lsb, for the 64kbps to 2mbps operating range 2mbps each lsb, for the 2mbps to 64mbps operating range 16mbps each lsb, for the 16mbps to 416mbps operating range
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 100 of 375 table 8-22. credit threshold settings with resulting bandwidths low-range cir mid-range cir high-range cir credit cir credit cir credit cir threshold bandwidth threshold bandwidth threshold bandwidth 243 64.04e+3 249 2.00e+6 249 16.00e+6 121 128.07e+3 124 4.00e+6 124 32.00e+6 80 192.90e+3 82 6.02e+6 82 48.19e+6 60 256.15e+3 62 7.94e+6 62 63.49e+6 48 318.88e+3 49 10.00e+6 49 80.00e+6 40 381.10e+3 41 11.90e+6 41 95.24e+6 34 446.43e+3 35 13.89e+6 35 111.11e+6 30 504.03e+3 30 16.13e+6 30 129.03e+6 26 578.70e+3 27 17.86e+6 27 142.86e+6 23 651.04e+3 26 18.52e+6 26 148.15e+6 21 710.23e+3 22 21.74e+6 22 173.91e+6 19 781.25e+3 20 23.81e+6 20 190.48e+6 18 822.37e+3 18 26.32e+6 18 210.53e+6 16 919.12e+3 17 27.78e+6 17 222.22e+6 15 976.56e+3 16 29.41e+6 16 235.29e+6 14 1.04e+6 15 31.25e+6 15 250.00e+6 13 1.12e+6 14 33.33e+6 14 266.67e+6 12 1.20e+6 13 35.71e+6 13 285.71e+6 11 1.30e+6 12 38.46e+6 12 307.69e+6 10 1.42e+6 11 41.67e+6 11 333.33e+6 9 1.56e+6 10 45.45e+6 10 363.64e+6 9 1.56e+6 9 50.00e+6 9 400.00e+6 8 1.74e+6 8 55.56e+6 7 1.95e+6 7 62.50e+6
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 101 of 375 9. applications information 9.1 interfacing to maxim t1/e1 transceivers the devices in the DS33X162 product fa mily can be seamlessly connected to maxim t1/e1 transceivers, without the need for additional external components. the diagram below depicts the electrical connections between the devices. figure 9-1. interfacing with t1/e1 transceivers figure 9-2. example functional timing: ds2155 e1 transmit-side boundary timing * note ds2155 tclk shown only for comparative purposes. tser(i) tchclk(o) tsync(o) maxim t1/e1 transceiver rser(o) rchclk(o) rsync(o) tdata(o) tclk(i) tsync(i) DS33X162/x82/x81 /x42/x41/x11/w41 /w11 rdata(i) rclk(i) rsync(i) lsb msb lsb msb lsb msb framing byte / channel 0 channel 1 tclk tser tsync tchclk
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 102 of 375 figure 9-3. example functional timing: ds2155 t1 transmit-side boundary timing * note ds2155 tclk shown only for comparative purposes. figure 9-4. example functional timing: ds2155 e1 receive-side boundary timing * note ds2155 rclk shown only for comparative purposes. figure 9-5. example functional timing: ds2155 t1 receive-side boundary timing * note ds2155 rclk shown only for comparative purposes. when interfacing to a maxim t1/e1 transceiver as shown, the device should be programmed to invert the rclk input for each serial interface ( li.rcr1.rclkinv = 1). because the first gapped transmit clock input edge after the tr ansmit sync pulse is coincident with the start of the first byte of user data, the transmit sync setup control bi ts must be configured for a sync pulse that arrives zero clock cycles early ( li.tcr.ts_setup[1:0] = 00). lsb x msb lsb msb lsb msb time slot 1 time slot 2 tclk tser tsync tchclk channel 32 framing byte / channel 0 channel 1 rclk rser rsync lsb msb msb lsb rchclk time slot 24 time slot 1 time slot 2 rclk rser rsync lsb msb msb lsb rchclk f
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 103 of 375 9.2 interfacing to maxim t3/e3 transceivers the devices in the DS33X162 product fa mily can be seamlessly connected to maxim t3/e3 transceivers, without the need for additional external components. the diagram below depicts the electrical connections between the devices. figure 9-6. interfacing with t3/e3 transceivers figure 9-7. example functional timing: ds3170 ds3 transmit-side boundary timing tser(i) tgclk(o) tsofo(o) dallas semiconductor t3/e3 transceiver rser(o) rgclk(o) rsofo(o) tdata(o) tclk(i) tsync(i) DS33X162/x82/x81 /x42/x41/x11/w41 /w11 rdata(i) rclk(i) rsync(i)
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 104 of 375 figure 9-8. example functional timing: ds3170 ds3 receive-side boundary timing rclko or rclki ds3 rser ds3 rden rsofo ds3 rgclk x1 6 7 8 9 10 11 12 13 12345 1415 because the third gapped transmit clock input edge after the tr ansmit sync pulse is coincident with the start of the first byte of user data, the transmit sync setup control bi ts must be configured for a sync pulse that arrives three clock cycles early ( li.tcr .ts_setup[1:0] = 11).
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 105 of 375 10. device registers eleven address bits are used address the regi ster space. the register map is shown in table 10-1. the addressable range is 000h-7ffh. register address location s are shared across the product family to preserve software compatibility. the serial interface (line) registers are used to configure the serial port and the associated transport protocol. the ethernet interface (subscriber) re gisters are used to control and observe each of the ethernet ports. the registers associated with the mac must be configured through indirect register write /read access due to the architecture of the device. when writing to a register input values for unused bits and registers (those designated with ???) should be zero unless specifically noted otherwise, as these bits and r egisters are reserved. when a register is read from, the values of the unused bits and register s should be ignored. a latched status bi t is set when an event happens and is cleared when read. note that although most registers are defined as 16-bit registers, the constituent by tes are accessed through the parallel or spi interfaces one byte at a time. individual address locations are defined for each byte. the register details are provided in the following tables. table 10-1. register address map register address range global registers 000h ? 01fh microport block 020h ? 03fh mac 1 port 040h ? 05fh mac 2 port 060h ? 07fh common vlan table 080h ? 09fh transmit lan 0a0h ? 0bfh receive lan 0c0h ? 0ffh buffer manager 100h ? 1ffh packet processors (encapsulators) 200h ? 2ffh packet processors (decapsulators) 300h ? 3ffh transmit vcat/lcas 400h ? 4ffh receive vcat/lcas 500h ? 5ffh serial ports ? global 600h ? 63fh serial ports ? transmit & voice 640h ? 6ffh serial ports ? receive & voice 740h ? 7ffh
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 106 of 375 10.1 register bit maps 10.1.1 global register bit map table 10-2. global register bit map a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 global registers 000h wp4 wp3 wp2 wp1 wp0 gbe mp1 mp0 001h gl.idr rev2 rev1 rev0 spis vc2 vc1 vc0 vcat 002h - - - - - fmc-2 fmc-1 fmc-0 003h gl.cr1 - - p2spd0 - p1spd - - - 004h - - - - intm endel - rst 005h gl.cr2 - - - - - - - - 008h - bufis - tspis decis1 ecis1 txlanis rxlanis 009h gl.isr micis decis4 decis3 decis2 ecis4 ecis3 ecis2 rvcatis 00ah - bufie - tspie decie1 ecie1 txlanie rxlanie 00bh gl.ier micie decie4 decie3 decie2 ecie4 ecie3 ecie2 rvcatie 00ch - - - - - - - - 00dh gl.mbsr - - - - dlock plock - - microport registers 020h - - - - - - fifo1 fifo0 021h gl.mcr1 - - - - - - - - 022h wilen7 wilen6 wilen5 wilen4 wilen3 wilen2 wilen1 wilen0 023h gl.mcr2 - - - - wilen11 wilen10 wilen9 wilen8 024h lilen7 lilen6 lilen5 lilen4 lilen3 lilen2 lilen1 lilen0 025h gl.mcr3 - - - - lilen11 lilen10 lilen9 lilen8 026h welen7 welen6 welen5 welen4 welen3 welen2 welen1 welen0 027h gl.msr1 - - - - welen11 welen10 welen9 welen8 028h lelen7 lelen6 lelen5 lelen4 lelen3 lelen2 lelen1 lelen0 029h gl.msr2 - - - - lelen11 lelen10 lelen9 lelen8 02ah - - - - lanea lanie wanea wanie 02bh gl.msr3 - - - - - - - - 02ch - - - - laneal laniel waneal waniel 02dh gl.mlsr3 - - - - - - - - 02eh - - - - laneaie lanieie waneaie wanieie 02fh gl.msier3 - - - - - - - - 030h wpkt7 wpkt6 wpkt5 wpkt4 wpkt3 wpkt2 wpkt1 wpkt0 031h gl.mfawr - - - - - - rd_dn wr_dn 032h rpkt7 rpkt6 rpkt5 rpkt4 rpkt3 rpkt2 rpkt1 rpkt0 033h gl.mfarr - - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 107 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 mac 1 interface port 040h su.mac1radl macra7 macra6 macra5 macra4 macra3 macra2 macra1 macra0 041h su.mac1radh macra15 macra14 macra13 macra12 macra11 macra10 macra9 macra8 042h su.mac1rd0 macrd7 macrd6 macrd5 macrd4 macrd3 macrd2 macrd1 macrd0 043h su.mac1rd1 macrd15 macrd14 macrd13 macrd12 macrd11 macrd10 macrd9 macrd8 044h su.mac1rd2 macrd23 macrd22 macrd21 macrd20 macrd19 macrd18 macrd17 macrd16 045h su.mac1rd3 macrd31 macrd30 macrd29 macrd28 macrd27 macrd26 macrd25 macrd24 046h su.mac1wd0 macwd7 macwd6 macwd5 macwd4 macwd3 macwd2 macwd1 macwd0 047h su.mac1wd1 macwd15 macwd14 macwd13 macwd12 macwd11 macwd10 macwd09 macwd08 048h su.mac1wd2 macwd23 macwd22 macwd21 macwd20 macwd19 macwd18 macwd17 macwd16 049h su.mac1wd3 macd31 macd30 macd29 macd28 macd27 macd26 macd25 macd24 04ah su.mac1awl macaw7 macaw6 macaw5 macaw4 macaw3 macaw2 macaw1 macaw0 04bh su.mac1awh macaw15 macaw14 macaw13 macaw12 macaw11 macaw10 macaw9 macaw8 04ch su.mac1rwc - - - - - - mcrw mcs mac 2 interface port 060h su.mac2radl macra7 macra6 macra5 macra4 macra3 macra2 macra1 macra0 061h su.mac2radh macra15 macra14 macra13 macra12 macra11 macra10 macra9 macra8 062h su.mac2rd0 macrd7 macrd6 macrd5 macrd4 macrd3 macrd2 macrd1 macrd0 063h su.mac2rd1 macrd15 macrd14 macrd13 macrd12 macrd11 macrd10 macrd9 macrd8 064h su.mac2rd2 macrd23 macrd22 macrd21 macrd20 macrd19 macrd18 macrd17 macrd16 065h su.mac2rd3 macrd31 macrd30 macrd29 macrd28 macrd27 macrd26 macrd25 macrd24 066h su.mac2wd0 macwd7 macwd6 macwd5 macwd4 macwd3 macwd2 macwd1 macwd0 067h su.mac2wd1 macwd15 macwd14 macwd13 macwd12 macwd11 macwd10 macwd09 macwd08 068h su.mac2wd2 macwd23 macwd22 macwd21 macwd20 macwd19 macwd18 macwd17 macwd16 069h su.mac2wd3 macd31 macd30 macd29 macd28 macd27 macd26 macd25 macd24 06ah su.mac2awl macaw7 macaw6 macaw5 macaw4 macaw3 macaw2 macaw1 macaw0 06bh su.mac2awh macaw15 macaw14 macaw13 macaw12 macaw11 macaw10 macaw9 macaw8 06ch su.mac2rwc - - - - - - mcrw mcs common vlan table control 080h - - - - - cte ci caim 081h su.vtc - - - - - - - - 082h vtaa8 vtaa7 vtaa6 vtaa5 vtaa4 vtaa3 vtaa2 vtaa1 083h su.vtaa - - - - vtaa12 vtaa11 vtaa10 vtaa9 084h - - wvefw wvqfw lvdw lvefw lvqfw2 lvqfw1 085h su.vtwd - - - - - - - - 086h - - wvefr wvqfr lvdr lvefr lvqfr2 lvqfr1 087h su.vtrd - - - - - - - - 088h vtsa8 vtsa7 vtsa6 vtsa5 vtsa4 vtsa3 vtsa2 vtsa1 089h su.vtsa - - - vtis vtsa12 vtsa11 vtsa10 vtsa9
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 108 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 transmit lan and wan extraction 0a0h wnvdf wefr weds2 weds1 wevit weett wedat weht 0a1h su.wem - - - - - - wmgmtt wbat 0a2h - - - wehth wehtl wehtp3 wehtp2 wehtp1 0a3h su.wehtp - - - - - - - - 0a4h weht8 weht7 weht6 weht5 weht4 weht3 weht2 weht1 0a5h su.weht weht16 weht15 weht14 weht13 weht12 weht11 weht10 weht9 0a6h wedal8 wedal7 wedal6 wedal5 wedal4 wedal3 wedal2 wedal1 0a7h su.wedal wedal16 wedal15 wedal14 wedal13 wedal12 wedal11 wedal10 wedal9 0a8h wedam8 wedam7 wedam6 wedam5 wedam4 wedam3 wedam2 wedam1 0a9h su.wedam wedam16 wedam15 wedam14 wedam13 wedam12 wedam11 wedam10 wedam9 0aah wedah8 wedah7 wedah6 wedah5 wedah4 wedah3 wedah2 wedah1 0abh su.wedah wedah16 wedah15 wedah14 wedah13 wedah12 wedah11 wedah10 wedah9 0ach wedax8 wedax7 wedax6 wedax5 wedax4 wedax3 wedax2 wedax1 0adh su.wedax - - - - - - - - 0aeh weet8 weet7 weet6 weet5 weet4 weet3 weet2 weet1 0afh su.weet weet16 weet15 weet14 weet13 weet12 weet11 weet10 weet9 0b2h wetpid8 wetpid7 wetpid6 wetpid5 wetpid4 wetpid3 wetpid2 wetpid1 0b3h su.wetpid wetpid16 wetpid15 wetpid14 wetpid13 wetpid12 wetpid11 wetpid10 wetpid9 0b4h - - - - - - - weos 0b5h su.wos - - - - - - - - 0b6h - - - lifr liip2 liip1 lip lie 0b7h su.lim - - - - lp2r lp1r lp2ce lp1ce 0b8h - - - - - - - weom 0b9h su.wom - - - - - - - - 0bah - ltcc3 ltcc2 ltcc1 ltcc0 ltexd ltufe ltdef 0bbh su.lp1xs lted ltjto ltff - ltloc ltncp ltlc ltec 0bch - ltcc3 ltcc2 ltcc1 ltcc0 ltexd ltufe ltdef 0bdh su.lp2xs lted ltjto ltff - ltloc ltncp ltlc ltec receive lan registers 0c0h - - - leeps levit leett ledat lpm 0c1h su.lpm - - - - - - lmgmtt lbat 0c2h ledal7 ledal6 ledal5 ledal4 ledal3 ledal2 ledal1 ledal0 0c3h su.ledal ledal15 ledal14 ledal13 ledal12 ledal11 ledal10 ledal9 ledal8 0c4h ledam7 ledam6 ledam5 ledam4 ledam3 ledam2 ledam1 ledam0 0c5h su.ledam ledam15 ledam14 ledam13 ledam12 ledam11 ledam10 ledam9 ledam8 0c6h ledah7 ledah6 ledah5 ledah4 ledah3 ledah2 ledah1 ledah0 0c7h su.ledah ledah15 ledah14 ledah13 ledah12 ledah11 ledah10 ledah9 ledah8 0c8h ledax7 ledax6 ledax5 ledax4 ledax3 ledax2 ledax1 ledax0 0c9h su.ledax - - - - - - - - 0cah su.leet leet7 leet6 leet5 leet4 leet3 leet2 leet1 leet0
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 109 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 0cbh leet15 leet14 leet13 leet12 leet11 leet10 leet9 leet8 0cch lp1mim lp1qom lp1fr lp1pf2 lp1pf1 lp1etf2 lp1etf1 lp1e 0cdh su.lp1c - - - - - - - - 0ceh lp2mim lp2qom lp2fr lp2pf2 lp2pf1 lp2etf2 lp2etf1 lp2e 0cfh su.lp2c - - - - - - - - 0d0h - - lnpdf2 lnpdf1 lnetdf4 lnetdf3 lnetdf2 lnetdf1 0d1h su.lnfc - - - - - - - - 0d2h lqxpc8 lqxpc7 lqxpc6 lqxpc5 lqxpc4 lqxp c3 lqxpc2 lqxpc1 0d3h su.lqxpc lqxpc16 lqxpc15 lqxpc14 lqxpc13 lqxpc12 lqxpc11 lqxpc10 lqxpc9 0d4h lqtpid8 lqtpid7 lqtpid6 lqtpid5 lqtpid4 lqtpid3 lqtpid2 lqtpid1 0d5h su.lqtpid lqtpid16 lqtpid15 lqtpid14 lqtpid13 lqtpid12 lqtpid11 lqtpid10 lqtpid9 0d6h - - - - lp2i lp1i liqos2 liqos1 0d7h su.liqos - - - - - - - - 0d8h mpl8 mpl7 mpl6 mpl5 mpl4 mpl3 mpl2 mpl1 0d9h su.mpl - - mpl14 mpl13 mpl12 mpl11 mpl10 mpl9 0dah l1pct8 l1pct7 l1pct6 l1pct5 l1pct4 l1pct3 l1pct2 l1pct1 0dbh su.l1pp cbss - - - l1pm2 l1pm1 l1pcr2 l1pcr1 0dch l2pct8 l2pct7 l2pct6 l2pct5 l2pct4 l2pct3 l2pct2 l2pct1 0ddh su.l2pp cbss - - - l2pm2 l2pm1 l2pcr2 l2pcr1 0deh - - - - - - pte ptaim 0dfh su.ptc - - - - - - - - 0e0h - ptpaa ptaa6 ptaa5 ptaa4 ptaa3 ptaa2 ptaa1 0e1h su.ptaa - - - - - - - - 0e2h - - - - - - lpqfw2 lpqfw1 0e3h su.ptwd - - - - - - - - 0e4h - - - - - - lpqfr2 lpqfr1 0e5h su.ptrd - - - - - - - - 0e6h ptis ptpsa ptsa6 ptsa5 ptsa4 ptsa3 ptsa2 ptsa1 0e7h su.ptsa - - - - - - - - 0e8h bfap8 bfap7 bfap6 bfap5 bfap4 bfap3 bfap2 bfap1 0e9h su.bfc - - - - - bftr bfe bfap9
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 110 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 buffer manager (arbiter) registers 100h lq1sa-8 lq1sa-7 lq1sa-6 lq1sa-5 lq1sa-4 lq1sa-3 lq1sa-2 lq1sa-1 101h ar.lq1sa - - - - - lq1qpr lq1sa-10 lq1sa-9 102h lq2sa-8 lq2sa-7 lq2sa-6 lq2sa-5 lq2sa-4 lq2sa-3 lq2sa-2 lq2sa-1 103h ar.lq2sa - - - - - lq2qpr lq2sa-10 lq2sa-9 104h lq3sa-8 lq3sa-7 lq3sa-6 lq3sa-5 lq3sa-4 lq3sa-3 lq3sa-2 lq3sa-1 105h ar.lq3sa - - - - - lq3qpr lq3sa-10 lq3sa-9 106h lq4sa-8 lq4sa-7 lq4sa-6 lq4sa-5 lq4sa-4 lq4sa-3 lq4sa-2 lq4sa-1 107h ar.lq4sa - - - - - lq4qpr lq4sa-10 lq4sa-9 108h lq5sa-8 lq5sa-7 lq5sa-6 lq5sa-5 lq5sa-4 lq5sa-3 lq5sa-2 lq5sa-1 109h ar.lq5sa - - - - - lq5qpr lq5sa-10 lq5sa-9 10ah lq6sa-8 lq6sa-7 lq6sa-6 lq6sa-5 lq6sa-4 lq6sa-3 lq6sa-2 lq6sa-1 10bh ar.lq6sa - - - - - lq6qpr lq6sa-10 lq6sa-9 10ch lq7sa-8 lq7sa-7 lq7sa-6 lq7sa-5 lq7sa-4 lq7sa-3 lq7sa-2 lq7sa-1 10dh ar.lq7sa - - - - - lq7qpr lq7sa-10 lq7sa-9 10eh lq8sa-8 lq8sa-7 lq8sa-6 lq8sa-5 lq8sa-4 lq8sa-3 lq8sa-2 lq8sa-1 10fh ar.lq8sa - - - - - lq8qpr lq8sa-10 lq8sa-9 110h lq9sa-8 lq9sa-7 lq9sa-6 lq9sa-5 lq9sa-4 lq9sa-3 lq9sa-2 lq9sa-1 111h ar.lq9sa - - - - - lq9qpr lq9sa-10 lq9sa-9 112h lq10sa-8 lq10sa-7 lq10sa-6 lq10sa-5 l q10sa-4 lq10sa-3 lq10sa-2 lq10sa-1 113h ar.lq10sa - - - - - lq10qpr lq10sa-10 lq10sa-9 114h lq11sa-8 lq11sa-7 lq11sa-6 lq11sa-5 l q11sa-4 lq11sa-3 lq11sa-2 lq11sa-1 115h ar.lq11sa - - - - - lq11qpr lq11sa-10 lq11sa-9 116h lq12sa-8 lq12sa-7 lq12sa-6 lq12sa-5 l q12sa-4 lq12sa-3 lq12sa-2 lq12sa-1 117h ar.lq12sa - - - - - lq12qpr lq12sa-10 lq12sa-9 118h lq13sa-8 lq13sa-7 lq13sa-6 lq13sa-5 l q13sa-4 lq13sa-3 lq13sa-2 lq13sa-1 119h ar.lq13sa - - - - - lq13qpr lq13sa-10 lq13sa-9 11ah lq14sa-8 lq14sa-7 lq14sa-6 lq14sa-5 l q14sa-4 lq14sa-3 lq14sa-2 lq14sa-1 11bh ar.lq14sa - - - - - lq14qpr lq14sa-10 lq14sa-9 11ch lq15sa-8 lq15sa-7 lq15sa-6 lq15sa-5 l q15sa-4 lq15sa-3 lq15sa-2 lq15sa-1 11dh ar.lq15sa - - - - - lq15qpr lq15sa-10 lq15sa-9 11eh lq16sa-8 lq16sa-7 lq16sa-6 lq16sa-5 l q16sa-4 lq16sa-3 lq16sa-2 lq16sa-1 11fh ar.lq16sa - - - - - lq16qpr lq16sa-10 lq16sa-9 120h lq1ea-8 lq1ea-7 lq1ea-6 lq1ea-5 lq1ea-4 lq1ea-3 lq1ea-2 lq1ea-1 121h ar.lq1ea - - - - - - lq1ea-10 lq1ea-9 122h lq2ea-8 lq2ea-7 lq2ea-6 lq2ea-5 lq2ea-4 lq2ea-3 lq2ea-2 lq2ea-1 123h ar.lq2ea - - - - - - lq2ea-10 lq2ea-9 124h lq3ea-8 lq3ea-7 lq3ea-6 lq3ea-5 lq3ea-4 lq3ea-3 lq3ea-2 lq3ea-1 125h ar.lq3ea - - - - - - lq3ea-10 lq3ea-9
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 111 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 126h lq4ea-8 lq4ea-7 lq4ea-6 lq4ea-5 lq4ea-4 lq4ea-3 lq4ea-2 lq4ea-1 127h ar.lq4ea - - - - - - lq4ea-10 lq4ea-9 128h lq5ea-8 lq5ea-7 lq5ea-6 lq5ea-5 lq5ea-4 lq5ea-3 lq5ea-2 lq5ea-1 129h ar.lq5ea - - - - - - lq5ea-10 lq5ea-9 12ah lq6ea-8 lq6ea-7 lq6ea-6 lq6ea-5 lq6ea-4 lq6ea-3 lq6ea-2 lq6ea-1 12bh ar.lq6ea - - - - - - lq6ea-10 lq6ea-9 12ch lq7ea-8 lq7ea-7 lq7ea-6 lq7ea-5 lq7ea-4 lq7ea-3 lq7ea-2 lq7ea-1 12dh ar.lq7ea - - - - - - lq7ea-10 lq7ea-9 12eh lq8ea-8 lq8ea-7 lq8ea-6 lq8ea-5 lq8ea-4 lq8ea-3 lq8ea-2 lq8ea-1 12fh ar.lq8ea - - - - - - lq8ea-10 lq8ea-9 130h lq9ea-8 lq9ea-7 lq9ea-6 lq9ea-5 lq9ea-4 lq9ea-3 lq9ea-2 lq9ea-1 131h ar.lq9ea - - - - - - lq9ea-10 lq9ea-9 132h lq10ea-8 lq10ea-7 lq10ea-6 lq10ea-5 l q10ea-4 lq10ea-3 lq10ea-2 lq10ea-1 133h ar.lq10ea - - - - - - lq10ea-10 lq10ea-9 134h lq11ea-8 lq11ea-7 lq11ea-6 lq11ea-5 l q11ea-4 lq11ea-3 lq11ea-2 lq11ea-1 135h ar.lq11ea - - - - - - lq11ea-10 lq11ea-9 136h lq12ea-8 lq12ea-7 lq12ea-6 lq12ea-5 l q12ea-4 lq12ea-3 lq12ea-2 lq12ea-1 137h ar.lq12ea - - - - - - lq12ea-10 lq12ea-9 138h lq13ea-8 lq13ea-7 lq13ea-6 lq13ea-5 l q13ea-4 lq13ea-3 lq13ea-2 lq13ea-1 139h ar.lq13ea - - - - - - lq13ea-10 lq13ea-9 13ah lq14ea-8 lq14ea-7 lq14ea-6 lq14ea-5 l q14ea-4 lq14ea-3 lq14ea-2 lq14ea-1 13bh ar.lq14ea - - - - - - lq14ea-10 lq14ea-9 13ch lq15ea-8 lq15ea-7 lq15ea-6 lq15ea-5 l q15ea-4 lq15ea-3 lq15ea-2 lq15ea-1 13dh ar.lq15ea - - - - - - lq15ea-10 lq15ea-9 13eh lq16ea-8 lq16ea-7 lq16ea-6 lq16ea-5 l q16ea-4 lq16ea-3 lq16ea-2 lq16ea-1 13fh ar.lq16ea - - - - - - lq16ea-10 lq16ea-9 140h wq1sa-8 wq1sa-7 wq1sa-6 wq1sa-5 wq1sa-4 wq1sa-3 wq1sa-2 wq1sa-1 141h ar.wq1sa - - - - - wq1qpr wq1sa-10 wq1sa-9 142h wq2sa-8 wq2sa-7 wq2sa-6 wq2sa-5 wq2sa-4 wq2sa-3 wq2sa-2 wq2sa-1 143h ar.wq2sa - - - - - wq2qpr wq2sa-10 wq2sa-9 144h wq3sa-8 wq3sa-7 wq3sa-6 wq3sa-5 wq3sa-4 wq3sa-3 wq3sa-2 wq3sa-1 145h ar.wq3sa - - - - - wq3qpr wq3sa-10 wq3sa-9 146h wq4sa-8 wq4sa-7 wq4sa-6 wq4sa-5 wq4sa-4 wq4sa-3 wq4sa-2 wq4sa-1 147h ar.wq4sa - - - - - wq4qpr wq4sa-10 wq4sa-9 148h wq5sa-8 wq5sa-7 wq5sa-6 wq5sa-5 wq5sa-4 wq5sa-3 wq5sa-2 wq5sa-1 149h ar.wq5sa - - - - - wq5qpr wq5sa-10 wq5sa-9 14ah wq6sa-8 wq6sa-7 wq6sa-6 wq6sa-5 wq6sa-4 wq6sa-3 wq6sa-2 wq6sa-1 14bh ar.wq6sa - - - - - wq6qpr wq6sa-10 wq6sa-9 14ch wq7sa-8 wq7sa-7 wq7sa-6 wq7sa-5 wq7sa-4 wq7sa-3 wq7sa-2 wq7sa-1 14dh ar.wq7sa - - - - - wq7qpr wq7sa-10 wq7sa-9 14eh ar.wq8sa wq8sa-8 wq8sa-7 wq8sa-6 wq8sa-5 wq8sa-4 wq8sa-3 wq8sa-2 wq8sa-1
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 112 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 14fh - - - - - wq8qpr wq8sa-10 wq8sa-9 150h wq9sa-8 wq9sa-7 wq9sa-6 wq9sa-5 wq9sa-4 wq9sa-3 wq9sa-2 wq9sa-1 151h ar.wq9sa - - - - - wq9qpr wq9sa-10 wq9sa-9 152h wq10sa-8 wq10sa-7 wq10sa- 6 wq10sa-5 wq10sa-4 wq10sa-3 wq10sa-2 wq10sa-1 153h ar.wq10sa - - - - - wq10qpr wq10sa-10 wq10sa-9 154h wq11sa-8 wq11sa-7 wq11sa- 6 wq11sa-5 wq11sa-4 wq11sa-3 wq11sa-2 wq11sa-1 155h ar.wq11sa - - - - - wq11qpr wq11sa-10 wq11sa-9 156h wq12sa-8 wq12sa-7 wq12sa- 6 wq12sa-5 wq12sa-4 wq12sa-3 wq12sa-2 wq12sa-1 157h ar.wq12sa - - - - - wq12qpr wq12sa-10 wq12sa-9 158h wq13sa-8 wq13sa-7 wq13sa- 6 wq13sa-5 wq13sa-4 wq13sa-3 wq13sa-2 wq13sa-1 159h ar.wq13sa - - - - - wq13qpr wq13sa-10 wq13sa-9 15ah wq14sa-8 wq14sa-7 wq14sa- 6 wq14sa-5 wq14sa-4 wq14sa-3 wq14sa-2 wq14sa-1 15bh ar.wq14sa - - - - - wq14qpr wq14sa-10 wq14sa-9 15ch wq15sa-8 wq15sa-7 wq15sa- 6 wq15sa-5 wq15sa-4 wq15sa-3 wq15sa-2 wq15sa-1 15dh ar.wq15sa - - - - - wq15qpr wq15sa-10 wq15sa-9 15eh wq16sa-8 wq16sa-7 wq16sa- 6 wq16sa-5 wq16sa-4 wq16sa-3 wq16sa-2 wq16sa-1 15fh ar.wq16sa - - - - - wq16qpr wq16sa-10 wq16sa-9 160h wq1ea-8 wq1ea-7 wq1ea-6 wq1ea-5 wq1ea-4 wq1ea-3 wq1ea-2 wq1ea-1 161h ar.wq1ea - - - - - - wq1ea-10 wq1ea-9 162h wq2ea-8 wq2ea-7 wq2ea-6 wq2ea-5 wq2ea-4 wq2ea-3 wq2ea-2 wq2ea-1 163h ar.wq2ea - - - - - - wq2ea-10 wq2ea-9 164h wq3ea-8 wq3ea-7 wq3ea-6 wq3ea-5 wq3ea-4 wq3ea-3 wq3ea-2 wq3ea-1 165h ar.wq3ea - - - - - - wq3ea-10 wq3ea-9 166h wq4ea-8 wq4ea-7 wq4ea-6 wq4ea-5 wq4ea-4 wq4ea-3 wq4ea-2 wq4ea-1 167h ar.wq4ea - - - - - - wq4ea-10 wq4ea-9 168h wq5ea-8 wq5ea-7 wq5ea-6 wq5ea-5 wq5ea-4 wq5ea-3 wq5ea-2 wq5ea-1 169h ar.wq5ea - - - - - - wq5ea-10 wq5ea-9 16ah wq6ea-8 wq6ea-7 wq6ea-6 wq6ea-5 wq6ea-4 wq6ea-3 wq6ea-2 wq6ea-1 16bh ar.wq6ea - - - - - - wq6ea-10 wq6ea-9 16ch wq7ea-8 wq7ea-7 wq7ea-6 wq7ea-5 wq7ea-4 wq7ea-3 wq7ea-2 wq7ea-1 16dh ar.wq7ea - - - - - - wq7ea-10 wq7ea-9 16eh wq8ea-8 wq8ea-7 wq8ea-6 wq8ea-5 wq8ea-4 wq8ea-3 wq8ea-2 wq8ea-1 16fh ar.wq8ea - - - - - - wq8ea-10 wq8ea-9 170h wq9ea-8 wq9ea-7 wq9ea-6 wq9ea-5 wq9ea-4 wq9ea-3 wq9ea-2 wq9ea-1 171h ar.wq9ea - - - - - - wq9ea-10 wq9ea-9 172h wq10ea-8 wq10ea-7 wq10ea- 6 wq10ea-5 wq10ea-4 wq10ea-3 wq10ea-2 wq10ea-1 173h ar.wq10ea - - - - - - wq10ea-10 wq10ea-9 174h wq11ea-8 wq11ea-7 wq11ea- 6 wq11ea-5 wq11ea-4 wq11ea-3 wq11ea-2 wq11ea-1 175h ar.wq11ea - - - - - - wq11ea-10 wq11ea-9 176h wq12ea-8 wq12ea-7 wq12ea- 6 wq12ea-5 wq12ea-4 wq12ea-3 wq12ea-2 wq12ea-1 177h ar.wq12ea - - - - - - wq12ea-10 wq12ea-9
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 113 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 178h wq13ea-8 wq13ea-7 wq13ea- 6 wq13ea-5 wq13ea-4 wq13ea-3 wq13ea-2 wq13ea-1 179h ar.wq13ea - - - - - - wq13ea-10 wq13ea-9 17ah wq14ea-8 wq14ea-7 wq14ea- 6 wq14ea-5 wq14ea-4 wq14ea-3 wq14ea-2 wq14ea-1 17bh ar.wq14ea - - - - - - wq14ea-10 wq14ea-9 17ch wq15ea-8 wq15ea-7 wq15ea- 6 wq15ea-5 wq15ea-4 wq15ea-3 wq15ea-2 wq15ea-1 17dh ar.wq15ea - - - - - - wq15ea-10 wq15ea-9 17eh wq16ea-8 wq16ea-7 wq16ea- 6 wq16ea-5 wq16ea-4 wq16ea-3 wq16ea-2 wq16ea-1 17fh ar.wq16ea - - - - - - wq16ea-10 wq16ea-9 180h liqsa-8 liqsa-7 liqsa- 6 liqsa-5 liqsa-4 liq sa-3 liqsa-2 liqsa-1 181h ar.liqsa - - - - - liqpr liqsa-10 liqsa-9 182h liqea-8 liqea-7 liqea- 6 liqea-5 liqea-4 liq ea-3 liqea-2 liqea-1 183h ar.liqea - - - - - - liqea-10 liqea-9 184h leqsa-8 leqsa-7 leqsa- 6 leqsa-5 leqsa-4 leq sa-3 leqsa-2 leqsa-1 185h ar.leqsa - - - - - leqpr leqsa-10 leqsa-9 186h leqea-8 leqea-7 leqea- 6 leqea-5 leqea-4 leq ea-3 leqea-2 leqea-1 187h ar.leqea - - - - - - leqea-10 leqea-9 188h wiqsa-8 wiqsa-7 wiqsa-6 wiqsa-5 wiqsa-4 wiqsa-3 wiqsa-2 wiqsa-1 189h ar.wiqsa - - - - - wiqpr wiqsa-10 wiqsa-9 18ah wiqea-8 wiqea-7 wiqea-6 wiqea-5 wiqea-4 wiqea-3 wiqea-2 wiqea-1 18bh ar.wiqea - - - - - - wiqea-10 wiqea-9 18ch weqsa-8 weqsa-7 weqsa-6 weqsa-5 weqsa-4 weqsa-3 weqsa-2 weqsa-1 18dh ar.weqsa - - - - - weqpr weqsa-10 weqsa-9 18eh weqea-8 weqea-7 weqea-6 weqea-5 weqea-4 weqea-3 weqea-2 weqea-1 18fh ar.weqea - - - - - - weqea-10 weqea-9 190h lqw-8 lqw-7 lqw-6 lqw-5 lqw-4 lqw-3 lqw-2 lqw-1 191h ar.lqw - - - lqw-13 lqw-12 lqw-11 lqw-10 lqw-9 192h wirrw2 wirrw1 wienc2 wienc-1 wispl wiena wqpd asqpr 193h ar.mqc - - - - - - fpepd wqode 194h lq4rrw-2 lq4rrw-1 lq3rrw-2 lq3rrw -1 lq2rrw-2 lq2rrw-1 lq1rrw-2 lq1rrw-1 195h ar.lqsc - - - - - - - lqsm 196h bftoa-8 bftoa-7 bftoa- 6 bftoa-5 bftoa-4 bfto a-3 bftoa-2 bftoa-1 197h ar.bftoa - - - - - - bftoa-10 bftoa-9 198h lqos-8 lqos-7 lqos-6 lqos-5 lqos-4 lqos-3 lqos-2 lqos-1 199h ar.lqos lqos-16 lqos-15 lqos-14 lqos-13 lqos-12 lqos-11 lqos-10 lqos-9 19ah lqoim-8 lqoim-7 lqoim-6 lqoim-5 lqoim-4 lqoim-3 lqoim-2 lqoim-1 19bh ar.lqoim lqoim-16 lqoim-15 lqoim-14 lqoim-13 lqoim-12 lqoim-11 lqoim-10 lqoim-9 19ch lqnfs-8 lqnfs-7 lqnfs-6 lqnfs-5 lqnfs-4 lqnfs-3 lqnfs-2 lqnfs-1 19dh ar.lqnfs lqnfs-16 lqnfs-15 lqnfs-14 lqnfs-13 lqnfs-12 lqnfs-11 lqnfs-10 lqnfs-9 19eh lqnfim-8 lqnfim-7 lqnfim-6 lqnfim-5 lqnfim-4 lqnfim-3 lqnfim-2 lqnfim-1 19fh ar.lqnfim lqnfim-16 lqnfim-15 lqnfim-14 lqnfim-13 lqnfim-12 lqnfim-11 lqnfim-10 lqnfim-9 1a0h ar.wqos wqos-8 wqos-7 wqos-6 wqos-5 wqos-4 wqos-3 wqos-2 wqos-1
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 114 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 1a1h wqos-16 wqos-15 wqos-14 wqos-13 wqos-12 wqos-11 wqos-10 wqos-9 1a2h wqoim-8 wqoim-7 wqoim-6 wqoim-5 wqoim-4 wqoim-3 wqoim-2 wqoim-1 1a3h ar.wqoim wqoim-16 wqoim-15 wqoim-14 wqoim-13 wqoim-12 wqoim-11 wqoim-10 wqoim-9 1a4h wqnfs-8 wqnfs-7 wqnfs-6 wqnfs-5 wqnfs-4 wqnfs-3 wqnfs-2 wqnfs-1 1a5h ar.wqnfs wqnfs-16 wqnfs-15 wqnfs-14 wqnfs-13 wqnfs-12 wqnfs-11 wqnfs-10 wqnfs-9 1a6h wqnfim-8 wqnfim-7 wqnfim-6 wqnfim-5 wqnfim-4 wqnfim-3 wqnfim-2 wqnfim-1 1a7h ar.wqnfim wqnfim-16 wqnfim-15 wqnfim-14 wqnfim-13 wqnfim-12 wqnfim-11 wqnfim-10 wqnfim-9 1a8h - - - - - - weqos leqos 1a9h ar.eqos - - - - - - - - 1aah - - - - - - weqoim leqoim 1abh ar.eqoim - - - - - - - - 1ach - - - eqoi wqnfi wqoi lcnfi lqoi 1adh ar.bmis - - - - - - - - packet processor 1(encapsulator 1) 200h eiis elhde et1e et2e ere1 ere0 tbre ehcbo 201h pp.emcr egcm eprtsel efcsad ecfcrd efcs3216s - efcsb ebbys 202h elhd23 elhd22 elhd21 elhd20 elhd19 elhd18 elhd17 elhd16 203h pp.elhhr elhd31 elhd30 elhd29 elhd28 elhd27 elhd26 elhd25 elhd24 204h elhd7 elhd6 elhd 5 elhd4 elhd3 elhd2 elhd1 elhd0 205h pp.elhlr elhd15 elhd14 elhd13 elhd12 elhd11 elhd10 elhd9 elhd8 206h et1d23 et1d22 et1d21 et1d20 et1d19 et1d18 et1d17 et1d16 207h pp.et1dhr et1d31 et1d30 et1d29 et1d28 et1d27 et1d26 et1d25 et1d24 208h et1d7 et1d6 et1d5 et1d4 et1d3 et1d2 et1d1 et1d0 209h pp.et1dlr et1d15 et1d14 et1d13 et1d12 et1d11 et1d10 et1d9 et1d8 20ah et2d23 et2d22 et2d21 et2d20 et2d19 et2d18 et2d17 et2d16 20bh pp.et2dhr et2d31 et2d30 et2d29 et2d28 et2d27 et2d26 et2d25 et2d24 20ch et2d7 et2d6 et2d5 et2d4 et2d3 et2d2 et2d1 et2d0 20dh pp.et2dlr et2d15 et2d14 et2d13 et2d12 et2d11 et2d10 et2d9 et2d8 20eh eei5 eei4 eei3 eei2 eei1 eei0 esei - 20fh pp.eeir eplieie edeie eefcseie efcfeie ebdec1 ebdec0 eei7 eei6 210h efcnt7 efcnt6 efcnt5 efcnt4 efcnt3 efcnt2 efcnt1 efcnt0 211h pp.efclsr efcnt15 efcnt14 efcnt13 efcnt12 efcnt11 efcnt10 efcnt9 efcnt8 21eh eople eopse - fuf fovf flok ff fe 21fh pp.esmls - - - - sople sopse cople copse 220h eopleie eopseie - fufie fovfie flokie ffie feie 221h pp.esmie - - - - sopleie sopseie copleie copseie 226h ehfl7 ehfl6 ehfl5 ehfl4 ehfl3 ehfl2 ehfl1 ehfl0 227h pp.ehfl - - - - - - - - packet processor 2(encapsulator 2) 240h eiis elhde et1e et2e ere1 ere0 tbre ehcbo 241h pp.emcr egcm eprtsel efcsad ecfcrd efcs16en - efcsb ebbys
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 115 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 242h elhd23 elhd22 elhd21 elhd20 elhd19 elhd18 elhd17 elhd16 243h pp.elhhr elhd31 elhd30 elhd29 elhd28 elhd27 elhd26 elhd25 elhd24 244h elhd7 elhd6 elhd 5 elhd4 elhd3 elhd2 elhd1 elhd0 245h pp.elhlr elhd15 elhd14 elhd13 elhd12 elhd11 elhd10 elhd9 elhd8 246h et1d23 et1d22 et1d21 et1d20 et1d19 et1d18 et1d17 et1d16 247h pp.et1dhr et1d31 et1d30 et1d29 et1d28 et1d27 et1d26 et1d25 et1d24 248h et1d7 et1d6 et1d5 et1d4 et1d3 et1d2 et1d1 et1d0 249h pp.et1dlr et1d15 et1d14 et1d13 et1d12 et1d11 et1d10 et1d9 et1d8 24ah et2d23 et2d22 et2d21 et2d20 et2d19 et2d18 et2d17 et2d16 24bh pp.et2dhr et2d31 et2d30 et2d29 et2d28 et2d27 et2d26 et2d25 et2d24 24ch et2d7 et2d6 et2d5 et2d4 et2d3 et2d2 et2d1 et2d0 24dh pp.et2dlr et2d15 et2d14 et2d13 et2d12 et2d11 et2d10 et2d9 et2d8 24eh eei5 eei4 eei3 eei2 eei1 eei0 esei - 24fh pp.eeir eplieie edeie eefcseie efcfeie ebdec1 ebdec0 eei7 eei6 250h efcnt7 efcnt6 efcnt5 efcnt4 efcnt3 efcnt2 efcnt1 efcnt0 251h pp.efclsr efcnt15 efcnt14 efcnt13 efcnt12 efcnt11 efcnt10 efcnt9 efcnt8 25eh eople eopse - fuf fovf flok ff fe 25fh pp.esmls - - - - sople sopse cople copse 260h eopleie eopseie - fufie fovfie flokie ffie feie 261h pp.esmie - - - - sopleie sopseie copleie copseie 266h ehfl7 ehfl6 ehfl5 ehfl4 ehfl3 ehfl2 ehfl1 ehfl0 267h pp.ehfl - - - - - - - - packet processor 3 (encapsulator 3) 280h eiis elhde et1e et2e ere1 ere0 tbre ehcbo 281h pp.emcr egcm eprtsel efcsad ecfcrd efcs16en - efcsb ebbys 282h elhd23 elhd22 elhd21 elhd20 elhd19 elhd18 elhd17 elhd16 283h pp.elhhr elhd31 elhd30 elhd29 elhd28 elhd27 elhd26 elhd25 elhd24 284h elhd7 elhd6 elhd 5 elhd4 elhd3 elhd2 elhd1 elhd0 285h pp.elhlr elhd15 elhd14 elhd13 elhd12 elhd11 elhd10 elhd9 elhd8 286h et1d23 et1d22 et1d21 et1d20 et1d19 et1d18 et1d17 et1d16 287h pp.et1dhr et1d31 et1d30 et1d29 et1d28 et1d27 et1d26 et1d25 et1d24 288h et1d7 et1d6 et1d5 et1d4 et1d3 et1d2 et1d1 et1d0 289h pp.et1dlr et1d15 et1d14 et1d13 et1d12 et1d11 et1d10 et1d9 et1d8 28ah et2d23 et2d22 et2d21 et2d20 et2d19 et2d18 et2d17 et2d16 28bh pp.et2dhr et2d31 et2d30 et2d29 et2d28 et2d27 et2d26 et2d25 et2d24 28ch et2d7 et2d6 et2d5 et2d4 et2d3 et2d2 et2d1 et2d0 28dh pp.et2dlr et2d15 et2d14 et2d13 et2d12 et2d11 et2d10 et2d9 et2d8 28eh eei5 eei4 eei3 eei2 eei1 eei0 esei - 28fh pp.eeir eplieie edeie eefcseie efcfeie ebdec1 ebdec0 eei7 eei6 290h efcnt7 efcnt6 efcnt5 efcnt4 efcnt3 efcnt2 efcnt1 efcnt0 291h pp.efclsr efcnt15 efcnt14 efcnt13 efcnt12 efcnt11 efcnt10 efcnt9 efcnt8
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 116 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 29eh eople eopse - fuf fovf flok ff fe 29fh pp.esmls - - - - sople sopse cople copse 2a0h eopleie eopseie - fufie fovfie flokie ffie feie 2a1h pp.esmie - - - - sopleie sopseie copleie copseie 2a6h ehfl7 ehfl6 ehfl5 ehfl4 ehfl3 ehfl2 ehfl1 ehfl0 2a7h pp.ehfl - - - - - - - - packet processor 4(encapsulator 4) 2c0h eiis elhde et1e et2e ere1 ere0 tbre ehcbo 2c1h pp.emcr egcm eprtsel efcsad ecfcrd efcs16en - efcsb ebbys 2c2h elhd23 elhd22 elhd21 elhd20 elhd19 elhd18 elhd17 elhd16 2c3h pp.elhhr elhd31 elhd30 elhd29 elhd28 elhd27 elhd26 elhd25 elhd24 2c4h elhd7 elhd6 elhd 5 elhd4 elhd3 elhd2 elhd1 elhd0 2c5h pp.elhlr elhd15 elhd14 elhd13 elhd12 elhd11 elhd10 elhd9 elhd8 2c6h et1d23 et1d22 et1d21 et1d20 et1d19 et1d18 et1d17 et1d16 2c7h pp.et1dhr et1d31 et1d30 et1d29 et1d28 et1d27 et1d26 et1d25 et1d24 2c8h et1d7 et1d6 et1d5 et1d4 et1d3 et1d2 et1d1 et1d0 2c9h pp.et1dlr et1d15 et1d14 et1d13 et1d12 et1d11 et1d10 et1d9 et1d8 2cah et2d23 et2d22 et2d21 et2d20 et2d19 et2d18 et2d17 et2d16 2cbh pp.et2dhr et2d31 et2d30 et2d29 et2d28 et2d27 et2d26 et2d25 et2d24 2cch et2d7 et2d6 et2d5 et2d4 et2d3 et2d2 et2d1 et2d0 2cdh pp.et2dlr et2d15 et2d14 et2d13 et2d12 et2d11 et2d10 et2d9 et2d8 2ceh eei5 eei4 eei3 eei2 eei1 eei0 esei - 2cfh pp.eeir eplieie edeie eefcseie efcfeie ebdec1 ebdec0 eei7 eei6 2d0h efcnt7 efcnt6 efcnt5 efcnt4 efcnt3 efcnt2 efcnt1 efcnt0 2d1h pp.efclsr efcnt15 efcnt14 efcnt13 efcnt12 efcnt11 efcnt10 efcnt9 efcnt8 2deh eople eopse - fuf fovf flok ff fe 2dfh pp.esmls - - - - sople sopse cople copse 2e0h eopleie eopseie - fufie fovfie flokie ffie feie 2e1h pp.esmie - - - - sopleie sopseie copleie copseie 2e6h ehfl7 ehfl6 ehfl5 ehfl4 ehfl3 ehfl2 ehfl1 ehfl0 2e7h pp.ehfl - - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 117 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 packet processor 1(decapsulator 1) 300h dr1e dr2e dr3e dae1 dae0 dgsc dhrae dhcbo 301h pp.dmcr dgcm dprtsel dfcsad dcfcrd dfcs16en - dbbs rbre 302h d1d7d d1d6d d1d5d d1d4d d1d3d d1d2d d1d1d d1d0d 303h pp.da1dr d1d15d d1d14d d1d13d d1d12d d1d11d d1d10d d1d9d d1d8d 304h d2d7d d2d6d d2d5d d2d4d d2d3d d2d2d d2d1d d2d0d 305h pp.da2dr d2d15d d2d14d d2d13d d2d12d d2d11d d2d10d d2d9d d2d8d 306h d3d7d d3d6d d3d5d d3d4d d3d3d d3d2d d3d1d d3d0d 307h pp.da3dr d3d15d d3d14d d3d13d d3d12d d3d11d d3d10d d3d9d d3d8d 308h d4d7d d4d6d d4d5d d4d4d d4d3d d4d2d d4d1d d4d0d 309h pp.da4dr d4d15d d4d14d d4d13d d4d12d d4d11d d4d10d d4d9d d4d8d 30ah d5d7d d5d6d d5d5d d5d4d d5d3d d5d2d d5d1d d5d0d 30bh pp.da5dr d5d15d d5d14d d5d13d d5d12d d5d11d d5d10d d5d9d d5d8d 30ch d6d7d d6d6d d6d5d d6d4d d6d3d d6d2d d6d1d d6d0d 30dh pp.da6dr d6d15d d6d14d d6d13d d6d12d d6d11d d6d10d d6d9d d6d8d 30eh d7d7d d7d6d d7d5d d7d4d d7d3d d7d2d d7d1d d7d0d 30fh pp.da7dr d7d15d d7d14d d7d13d d7d12d d7d11d d7d10d d7d9d d7d8d 310h d8d7d d8d6d d8d5d d8d4d d8d3d d8d2d d8d1d d8d0d 311h pp.da8dr d8d15d d8d14d d8d13d d8d12d d8d11d d8d10d d8d9d d8d8d 312h d9d7d d9d6d d9d5d d9d4d d9d3d d9d2d d9d1d d9d0d 313h pp.da9dr d9d15d d9d14d d9d13d d9d12d d9d11d d9d10d d9d9d d9d8d 314h dfur dfovf - - - - - - 315h pp.dmlsr dgsls dgslls dglcls dglcsls dffls - dchecfls dtchecfls 316h dfurie dfovfie - - - - - - 317h pp.dmlsie dgsie dgslie dglcie dglcsie dffie - dchecfie dtchecfie 318h dgplc7 dgplc6 dgplc5 dgplc4 dgplc3 dgplc2 dgplc1 dgplc0 319h pp.dgplc dgplc15 dgplc14 dgplc13 dgplc12 dg plc11 dgplc10 dgplc9 dgplc8 31ah dbplc7 dbplc6 dbplc5 dbplc4 dbplc3 dbpl c2 dbplc1 dbplc0 31bh pp.dgblc dbplc15 dbplc14 dbplc13 dbplc12 d bplc11 dbplc10 dbplc9 dbplc8 31ch - - - - - dgsync dgpsync dghunt 31dh pp.dssr - - - - - - - - 31eh dhsr23 dhsr22 dhsr21 dhsr20 dhsr19 dhsr18 dhsr17 dhsr16 31fh pp.dhhsr dhsr31 dhsr30 dhsr29 dhsr28 dhsr27 dhsr26 dhsr25 dhsr24 320h dhsr7 dhsr6 dhsr5 dhsr4 dhsr3 dhsr2 dhsr1 dhsr0 321h pp.dhlsr dhsr15 dhsr14 dhsr13 dhsr12 dhsr11 dhsr10 dhsr9 dhsr8 322h - - - dem dsmre depre dfsrpwc 323h pp.dfscr - - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 118 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 packet processor 2 (decapsulator 2) 340h dr1e dr2e dr3e dae1 dae0 dgsc dhrae dhcbo 341h pp.dmcr dgcm dprtsel dfcsad dcfcrd dfcs16en - dbbs rbre 342h d1d7d d1d6d d1d5d d1d4d d1d3d d1d2d d1d1d d1d0d 343h pp.da1dr d1d15d d1d14d d1d13d d1d12d d1d11d d1d10d d1d9d d1d8d 344h d2d7d d2d6d d2d5d d2d4d d2d3d d2d2d d2d1d d2d0d 345h pp.da2dr d2d15d d2d14d d2d13d d2d12d d2d11d d2d10d d2d9d d2d8d 346h d3d7d d3d6d d3d5d d3d4d d3d3d d3d2d d3d1d d3d0d 347h pp.da3dr d3d15d d3d14d d3d13d d3d12d d3d11d d3d10d d3d9d d3d8d 348h d4d7d d4d6d d4d5d d4d4d d4d3d d4d2d d4d1d d4d0d 349h pp.da4dr d4d15d d4d14d d4d13d d4d12d d4d11d d4d10d d4d9d d4d8d 34ah d5d7d d5d6d d5d5d d5d4d d5d3d d5d2d d5d1d d5d0d 34bh pp.da5dr d5d15d d5d14d d5d13d d5d12d d5d11d d5d10d d5d9d d5d8d 34ch d6d7d d6d6d d6d5d d6d4d d6d3d d6d2d d6d1d d6d0d 34dh pp.da6dr d6d15d d6d14d d6d13d d6d12d d6d11d d6d10d d6d9d d6d8d 34eh d7d7d d7d6d d7d5d d7d4d d7d3d d7d2d d7d1d d7d0d 34fh pp.da7dr d7d15d d7d14d d7d13d d7d12d d7d11d d7d10d d7d9d d7d8d 350h d8d7d d8d6d d8d5d d8d4d d8d3d d8d2d d8d1d d8d0d 351h pp.da8dr d8d15d d8d14d d8d13d d8d12d d8d11d d8d10d d8d9d d8d8d 352h d9d7d d9d6d d9d5d d9d4d d9d3d d9d2d d9d1d d9d0d 353h pp.da9dr d9d15d d9d14d d9d13d d9d12d d9d11d d9d10d d9d9d d9d8d 354h dfur dfovf - - - - - - 355h pp.dmlsr dgsls dgslls dglcls dglcsls dffls - dchecfls dtchecfls 356h dfurie dfovfie - - - - - - 357h pp.dmlsie dgsie dgslie dglcie dglcsie dffie - dchecfi e dtchecfie 358h dgplc7 dgplc6 dgplc5 dgplc4 dgplc3 dgplc2 dgplc1 dgplc0 359h pp.dgplc dgplc15 dgplc14 dgplc13 dgplc12 dgplc11 dgplc10 dgplc9 dgplc8 35ah dbplc7 dbplc6 dbpl c5 dbplc4 dbplc3 dbpl c2 dbplc1 dbplc0 35bh pp.dgblc dbplc15 dbplc14 dbplc13 dbplc1 2 dbplc11 dbplc10 dbplc9 dbplc8 35ch - - - - - dgsync dgpsync dghunt 35dh pp.dssr - - - - - - - - 35eh dhsr23 dhsr22 dhsr21 dhsr20 dhsr19 dhsr18 dhsr17 dhsr16 35fh pp.dhhsr dhsr31 dhsr30 dhsr29 dhsr28 dhsr27 dhsr26 dhsr25 dhsr24 360h dhsr7 dhsr6 dhsr5 dhsr4 dhsr3 dhsr2 dhsr1 dhsr0 361h pp.dhlsr dhsr15 dhsr14 dhsr13 dhsr12 dhsr11 dhsr10 dhsr9 dhsr8 362h - - - - dem dsmre depre dfsrpwc 363h pp.dfscr - - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 119 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 packet processor 3(decapsulator 3) 380h dr1e dr2e dr3e dae1 dae0 dgsc dhrae dhcbo 381h pp.dmcr dgcm dprtsel dfcsad dcfcrd dfcs16en - dbbs rbre 382h d1d7d d1d6d d1d5d d1d4d d1d3d d1d2d d1d1d d1d0d 383h pp.da1dr d1d15d d1d14d d1d13d d1d12d d1d11d d1d10d d1d9d d1d8d 384h d2d7d d2d6d d2d5d d2d4d d2d3d d2d2d d2d1d d2d0d 385h pp.da2dr d2d15d d2d14d d2d13d d2d12d d2d11d d2d10d d2d9d d2d8d 386h d3d7d d3d6d d3d5d d3d4d d3d3d d3d2d d3d1d d3d0d 387h pp.da3dr d3d15d d3d14d d3d13d d3d12d d3d11d d3d10d d3d9d d3d8d 388h d4d7d d4d6d d4d5d d4d4d d4d3d d4d2d d4d1d d4d0d 389h pp.da4dr d4d15d d4d14d d4d13d d4d12d d4d11d d4d10d d4d9d d4d8d 38ah d5d7d d5d6d d5d5d d5d4d d5d3d d5d2d d5d1d d5d0d 38bh pp.da5dr d5d15d d5d14d d5d13d d5d12d d5d11d d5d10d d5d9d d5d8d 38ch d6d7d d6d6d d6d5d d6d4d d6d3d d6d2d d6d1d d6d0d 38dh pp.da6dr d6d15d d6d14d d6d13d d6d12d d6d11d d6d10d d6d9d d6d8d 38eh d7d7d d7d6d d7d5d d7d4d d7d3d d7d2d d7d1d d7d0d 38fh pp.da7dr d7d15d d7d14d d7d13d d7d12d d7d11d d7d10d d7d9d d7d8d 390h d8d7d d8d6d d8d5d d8d4d d8d3d d8d2d d8d1d d8d0d 391h pp.da8dr d8d15d d8d14d d8d13d d8d12d d8d11d d8d10d d8d9d d8d8d 392h d9d7d d9d6d d9d5d d9d4d d9d3d d9d2d d9d1d d9d0d 393h pp.da9dr d9d15d d9d14d d9d13d d9d12d d9d11d d9d10d d9d9d d9d8d 394h dfur dfovf - - - - - - 395h pp.dmlsr dgsls dgslls dglcls dglcsls dffls - dchecfls dtchecfls 396h dfurie dfovfie - - - - - - 397h pp.dmlsie dgsie dgslie dglcie dglcsie dffie - dchecfi e dtchecfie 398h dgplc7 dgplc6 dgplc5 dgplc4 dgplc3 dgplc2 dgplc1 dgplc0 399h pp.dgplc dgplc15 dgplc14 dgplc13 dgplc12 dgplc11 dgplc10 dgplc9 dgplc8 39ah dbplc7 dbplc6 dbpl c5 dbplc4 dbplc3 dbpl c2 dbplc1 dbplc0 39bh pp.dgblc dbplc15 dbplc14 dbplc13 dbplc12 dbplc11 dbplc10 dbplc9 dbplc8 39ch - - - - - dgsync dgpsync dghunt 39dh pp.dssr - - - - - - - - 39eh dhsr23 dhsr22 dhsr21 dhsr20 dhsr19 dhsr18 dhsr17 dhsr16 39fh pp.dhhsr dhsr31 dhsr30 dhsr29 dhsr28 dhsr27 dhsr26 dhsr25 dhsr24 3a0h dhsr7 dhsr6 dhsr5 dhsr4 dhsr3 dhsr2 dhsr1 dhsr0 3a1h pp.dhlsr dhsr15 dhsr14 dhsr13 dhsr12 dhsr11 dhsr10 dhsr9 dhsr8 3a2h - - - - dem dsmre depre dfsrpwc 3a3h pp.dfscr - - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 120 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 packet processor 4(decapsulator 4) 3c0h dr1e dr2e dr3e dae1 dae0 dgsc dhrae dhcbo 3c1h pp.dmcr dgcm dprtsel dfcsad dcfcrd dfcs16en - dbbs rbre 3c2h d1d7d d1d6d d1d5d d1d4d d1d3d d1d2d d1d1d d1d0d 3c3h pp.da1dr d1d15d d1d14d d1d13d d1d12d d1d11d d1d10d d1d9d d1d8d 3c4h d2d7d d2d6d d2d5d d2d4d d2d3d d2d2d d2d1d d2d0d 3c5h pp.da2dr d2d15d d2d14d d2d13d d2d12d d2d11d d2d10d d2d9d d2d8d 3c6h d3d7d d3d6d d3d5d d3d4d d3d3d d3d2d d3d1d d3d0d 3c7h pp.da3dr d3d15d d3d14d d3d13d d3d12d d3d11d d3d10d d3d9d d3d8d 3c8h d4d7d d4d6d d4d5d d4d4d d4d3d d4d2d d4d1d d4d0d 3c9h pp.da4dr d4d15d d4d14d d4d13d d4d12d d4d11d d4d10d d4d9d d4d8d 3cah d5d7d d5d6d d5d5d d5d4d d5d3d d5d2d d5d1d d5d0d 3cbh pp.da5dr d5d15d d5d14d d5d13d d5d12d d5d11d d5d10d d5d9d d5d8d 3cch d6d7d d6d6d d6d5d d6d4d d6d3d d6d2d d6d1d d6d0d 3cdh pp.da6dr d6d15d d6d14d d6d13d d6d12d d6d11d d6d10d d6d9d d6d8d 3ceh d7d7d d7d6d d7d5d d7d4d d7d3d d7d2d d7d1d d7d0d 3cfh pp.da7dr d7d15d d7d14d d7d13d d7d12d d7d11d d7d10d d7d9d d7d8d 3d0h d8d7d d8d6d d8d5d d8d4d d8d3d d8d2d d8d1d d8d0d 3d1h pp.da8dr d8d15d d8d14d d8d13d d8d12d d8d11d d8d10d d8d9d d8d8d 3d2h d9d7d d9d6d d9d5d d9d4d d9d3d d9d2d d9d1d d9d0d 3d3h pp.da9dr d9d15d d9d14d d9d13d d9d12d d9d11d d9d10d d9d9d d9d8d 3d4h dfur dfovf - - - - - - 3d5h pp.dmlsr dgsls dgslls dglcls dglcsls dffls - dchecfls dtchecfls 3d6h dfurie dfovfie - - - - - - 3d7h pp.dmlsie dgsie dgslie dglcie dglcsie dffie - dchecfi e dtchecfie 3d8h dgplc7 dgplc6 dgplc5 dgplc4 dgplc3 dgplc2 dgplc1 dgplc0 3d9h pp.dgplc dgplc15 dgplc14 dgplc13 dgplc12 dg plc11 dgplc10 dgplc9 dgplc8 3dah dbplc7 dbplc6 dbplc5 dbplc4 dbplc3 dbpl c2 dbplc1 dbplc0 3dbh pp.dgblc dbplc15 dbplc14 dbplc13 dbplc12 d bplc11 dbplc10 dbplc9 dbplc8 3dch - - - - - dgsync dgpsync dghunt 3ddh pp.dssr - - - - - - - - 3deh dhsr23 dhsr22 dhsr21 dhsr20 dhsr19 dhsr18 dhsr17 dhsr16 3dfh pp.dhhsr dhsr31 dhsr30 dhsr29 dhsr28 dhsr27 dhsr26 dhsr25 dhsr24 3e0h dhsr7 dhsr6 dhsr5 dhsr4 dhsr3 dhsr2 dhsr1 dhsr0 3e1h pp.dhlsr dhsr15 dhsr14 dhsr13 dhsr12 dhsr11 dhsr10 dhsr9 dhsr8 3e2h - - - - dem dsmre depre dfsrpwc 3e3h pp.dfscr - - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 121 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 vcat / lcas transmit registers 400h v4fm1 v4fm0 v3fm1 v3fm0 v2fm1 v2fm0 v1fm1 v1fm0 401h vcat.tcr1 - - - - tgidbc tgidm tload tvblken 402h tv2mc3 tv2mc2 tv2mc1 tv2mc0 tv1mc3 tv1mc2 tv1mc1 tv1mc0 403h vcat.tcr2 tv4mc3 tv4mc2 tv4mc1 tv4mc0 tv3mc3 tv3mc2 tv3mc1 tv3mc0 406h - - - - rsack4 rsack3 rsack2 rsack1 407h vcat.tlcr1 - - - - - - - - 408h - - - - atmstd4 atmstd3 atmstd2 atmstd1 409h vcat.tlcr2 - - - - - - - - 40ah v1mst7 v1mst6 v1mst5 v1mst4 v1mst3 v1mst2 v1mst1 v1mst0 40bh vcat.tlcr3 v1mst15 v1mst14 v1mst13 v1mst12 v1mst11 v1mst10 v1mst9 v1mst8 40ch v2mst7 v2mst6 v2mst5 v2mst4 v2mst3 v2mst2 v2mst1 v2mst0 40dh vcat.tlcr4 v2mst15 v2mst14 v2mst13 v2mst12 v2mst11 v2mst10 v2mst9 v2mst8 40eh v3mst7 v3mst6 v3mst5 v3mst4 v3mst3 v3mst2 v3mst1 v3mst0 40fh vcat.tlcr5 v3mst15 v3mst14 v3mst13 v3mst12 v3mst11 v3mst10 v3mst9 v3mst8 410h v4mst7 v4mst6 v4mst5 v4mst4 v4mst3 v4mst2 v4mst1 v4mst0 411h vcat.tlcr6 v4mst15 v4mst14 v4mst13 v4mst12 v4mst11 v4mst10 v4mst9 v4mst8 420h - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 421h vcat.tcr3 (1) - - - - tvsq3 tvsq2 tvsq1 tvsq0 422h - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 423h vcat.tcr3 (2) - - - - tvsq3 tvsq2 tvsq1 tvsq0 424h - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 425h vcat.tcr3 (3) - - - - tvsq3 tvsq2 tvsq1 tvsq0 426h - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 427h vcat.tcr3 (4) - - - - tvsq3 tvsq2 tvsq1 tvsq0 428h - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 429h vcat.tcr3 (5) - - - - tvsq3 tvsq2 tvsq1 tvsq0 42ah - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 42bh vcat.tcr3 (6) - - - - tvsq3 tvsq2 tvsq1 tvsq0 42ch - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 42dh vcat.tcr3 (7) - - - - tvsq3 tvsq2 tvsq1 tvsq0 42eh - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 42fh vcat.tcr3 (8) - - - - tvsq3 tvsq2 tvsq1 tvsq0 430h - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 431h vcat.tcr3 (9) - - - - tvsq3 tvsq2 tvsq1 tvsq0 432h - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 433h vcat.tcr3 (10) - - - - tvsq3 tvsq2 tvsq1 tvsq0
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 122 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 434h - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 435h vcat.tcr3 (11) - - - - tvsq3 tvsq2 tvsq1 tvsq0 436h - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 437h vcat.tcr3 (12) - - - - tvsq3 tvsq2 tvsq1 tvsq0 438h - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 439h vcat.tcr3 (13) - - - - tvsq3 tvsq2 tvsq1 tvsq0 43ah - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 43bh vcat.tcr3 (14) - - - - tvsq3 tvsq2 tvsq1 tvsq0 43ch - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 43dh vcat.tcr3 (15) - - - - tvsq3 tvsq2 tvsq1 tvsq0 43eh - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa 43fh vcat.tcr3 (16) - - - - tvsq3 tvsq2 tvsq1 tvsq0 440h - - - - ctrl3 ctrl2 ctrl1 ctrl0 441h vcat.tlcr8(1) - - - - - - - - 442h - - - - ctrl3 ctrl2 ctrl1 ctrl0 443h vcat.tlcr8(2) - - - - - - - - 444h - - - - ctrl3 ctrl2 ctrl1 ctrl0 445h vcat.tlcr8(3) - - - - - - - - 446h - - - - ctrl3 ctrl2 ctrl1 ctrl0 447h vcat.tlcr8(4) - - - - - - - - 448h - - - - ctrl3 ctrl2 ctrl1 ctrl0 449h vcat.tlcr8(5) - - - - - - - - 44ah - - - - ctrl3 ctrl2 ctrl1 ctrl0 44bh vcat.tlcr8(6) - - - - - - - - 44ch - - - - ctrl3 ctrl2 ctrl1 ctrl0 44dh vcat.tlcr8(7) - - - - - - - - 44eh - - - - ctrl3 ctrl2 ctrl1 ctrl0 44fh vcat.tlcr8(8) - - - - - - - - 450h - - - - ctrl3 ctrl2 ctrl1 ctrl0 451h vcat.tlcr8(9) - - - - - - - - 452h - - - - ctrl3 ctrl2 ctrl1 ctrl0 453h vcat.tlcr8(10) - - - - - - - - 454h - - - - ctrl3 ctrl2 ctrl1 ctrl0 455h vcat.tlcr8(11) - - - - - - - - 456h - - - - ctrl3 ctrl2 ctrl1 ctrl0 457h vcat.tlcr8(12) - - - - - - - - 458h - - - - ctrl3 ctrl2 ctrl1 ctrl0 459h vcat.tlcr8(13) - - - - - - - - 45ah - - - - ctrl3 ctrl2 ctrl1 ctrl0 45bh vcat.tlcr8(14) - - - - - - - - 45ch vcat.tlcr8(15) - - - - ctrl3 ctrl2 ctrl1 ctrl0
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 123 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 45dh - - - - - - - - 45eh - - - - ctrl3 ctrl2 ctrl1 ctrl0 45fh vcat.tlcr8(16) - - - - - - - - 480h tgid7 tgid6 tgid5 tgid4 tgid3 tgid2 tgid1 tgid0 481h vcat.tcr4 (1) tgid15 tgid14 tgid13 tgid12 tgid11 tgid10 tgid9 tgid8 482h tgid7 tgid6 tgid5 tgid4 tgid3 tgid2 tgid1 tgid0 483h vcat.tcr4 (2) tgid15 tgid14 tgid13 tgid12 tgid11 tgid10 tgid9 tgid8 484h tgid7 tgid6 tgid5 tgid4 tgid3 tgid2 tgid1 tgid0 485h vcat.tcr4 (3) tgid15 tgid14 tgid13 tgid12 tgid11 tgid10 tgid9 tgid8 486h tgid7 tgid6 tgid5 tgid4 tgid3 tgid2 tgid1 tgid0 487h vcat.tcr4 (4) tgid15 tgid14 tgid13 tgid12 tgid11 tgid10 tgid9 tgid8 vcat / lcas receive registers 500h - - svintd t3t1wg4 t3t1wg3 t3t1wg2 t3t1wg1 rvblken 501h vcat.rcr1 - - - rven4 rgidbc rven3 rven2 rven1 502h le4 le3 le2 le1 realign4 realign3 realign2 realign1 503h vcat.rcr2 - - - - - - - - 504h rv2mc3 rv2mc2 rv2mc1 rv2mc0 rv1mc3 rv1mc2 rv1mc1 rv1mc0 505h vcat.rcr3 rv4mc3 rv4mc2 rv4mc1 rv4mc0 rv3mc3 rv3mc2 rv3mc1 rv3mc0 508h pisr8 pisr7 pisr6 pisr5 pisr4 pisr3 pisr2 pisr1 509h vcat.risr pisr16 pisr15 pisr14 pisr13 pisr12 pisr11 pisr10 pisr9 50ah v1mst7 v1mst6 v1mst5 v1mst4 v1mst3 v1mst2 v1mst1 v1mst0 50bh vcat.rlsr1 v1mst15 v1mst14 v1mst13 v1mst12 v1mst11 v1mst10 v1mst9 v1mst8 50ch v2mst7 v2mst6 v2mst5 v2mst4 v2mst3 v2mst2 v2mst1 v2mst0 50dh vcat.rlsr2 v2mst15 v2mst14 v2mst13 v2mst12 v2mst11 v2mst10 v2mst9 v2mst8 50eh v3mst7 v3mst6 v3mst5 v3mst4 v3mst3 v3mst2 v3mst1 v3mst0 50fh vcat.rlsr3 v3mst15 v3mst14 v3mst13 v3mst12 v3mst11 v3mst10 v3mst9 v3mst8 510h v4mst7 v4mst6 v4mst5 v4mst4 v4mst3 v4mst2 v4mst1 v4mst0 511h vcat.rlsr4 v4mst15 v4mst14 v4mst13 v4mst12 v4mst11 v4mst10 v4mst9 v4mst8 512h dde4 dde3 dde2 dde1 realignl4 realignl3 realignl2 realignl1 513h vcat.rrlsr - - - - vmstc4 vmstc3 vmstc2 vmstc1 514h vddeie4 vddeie3 vddeie2 vddeie1 realignie4 realignie3 realignie2 realignie1 515h vcat.rrsie - - - - vmstcie4 vmstcie3 vmstcie2 vmstcie1 530h rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 531h vcat.rcr4 (1) rfrst - - - - - - - 532h rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 533h vcat.rcr4 (2) rfrst - - - - - - - 534h rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 535h vcat.rcr4 (3) rfrst - - - - - - - 536h rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 537h vcat.rcr4 (4) rfrst - - - - - - - 538h vcat.rcr4 (5) rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 124 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 539h rfrst - - - - - - - 53ah rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 53bh vcat.rcr4 (6) rfrst - - - - - - - 53ch rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 53dh vcat.rcr4 (7) rfrst - - - - - - - 53eh rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 53fh vcat.rcr4 (8) rfrst - - - - - - - 540h rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 541h vcat.rcr4 (9) rfrst - - - - - - - 542h rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 543h vcat.rcr4 (10) rfrst - - - - - - - 544h rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 545h vcat.rcr4 (11) rfrst - - - - - - - 546h rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 547h vcat.rcr4 (12) rfrst - - - - - - - 548h rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 549h vcat.rcr4 (13) rfrst - - - - - - - 54ah rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 54bh vcat.rcr4 (14) rfrst - - - - - - - 54ch rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 54dh vcat.rcr4 (15) rfrst - - - - - - - 54eh rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa 54fh vcat.rcr4 (16) rfrst - - - - - - - 550h - - - rsack - - - lom 551h vcat.rsr1 (1) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 552h - - - rsack - - - lom 553h vcat.rsr1 (2) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 554h - - - rsack - - - lom 555h vcat.rsr1 (3) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 556h - - - rsack - - - lom 557h vcat.rsr1 (4) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 558h - - - rsack - - - lom 559h vcat.rsr1 (5) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 55ah - - - rsack - - - lom 55bh vcat.rsr1 (6) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 55ch - - - rsack - - - lom 55dh vcat.rsr1 (7) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 55eh - - - rsack - - - lom 55fh vcat.rsr1 (8) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 560h - - - rsack - - - lom 561h vcat.rsr1 (9) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 125 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 562h - - - rsack - - - lom 563h vcat.rsr1 (10) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 564h - - - rsack - - - lom 565h vcat.rsr1 (11) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 566h - - - rsack - - - lom 567h vcat.rsr1 (12) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 568h - - - rsack - - - lom 569h vcat.rsr1 (13) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 56ah - - - rsack - - - lom 56bh vcat.rsr1 (14) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 56ch - - - rsack - - - lom 56dh vcat.rsr1 (15) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 56eh - - - rsack - - - lom 56fh vcat.rsr1 (16) rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 570h - - - - crce gid semf emf 571h vcat.rsr2 (1) - - - - - - - - 572h - - - - crce gid semf emf 573h vcat.rsr2 (2) - - - - - - - - 574h - - - - crce gid semf emf 575h vcat.rsr2 (3) - - - - - - - - 576h - - - - crce gid semf emf 577h vcat.rsr2 (4) - - - - - - - - 578h - - - - crce gid semf emf 579h vcat.rsr2 (5) - - - - - - - - 57ah - - - - crce gid semf emf 57bh vcat.rsr2 (6) - - - - - - - - 57ch - - - - crce gid semf emf 57dh vcat.rsr2 (7) - - - - - - - - 57eh - - - - crce gid semf emf 57fh vcat.rsr2 (8) - - - - - - - - 580h - - - - crce gid semf emf 581h vcat.rsr2 (9) - - - - - - - - 582h - - - - crce gid semf emf 583h vcat.rsr2 (10) - - - - - - - - 584h - - - - crce gid semf emf 585h vcat.rsr2 (11) - - - - - - - - 586h - - - - crce gid semf emf 587h vcat.rsr2 (12) - - - - - - - - 588h - - - - crce gid semf emf 589h vcat.rsr2 (13) - - - - - - - - 58ah vcat.rsr2 (14) - - - - crce gid semf emf
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 126 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 58bh - - - - - - - - 58ch - - - - crce gid semf emf 58dh vcat.rsr2 (15) - - - - - - - - 58eh - - - - crce gid semf emf 58fh vcat.rsr2 (16) - - - - - - - - 590h - - - rsackl sql ctrl - loml 591h vcat.rslsr(1) - - - - - - - - 592h - - - rsackl sql ctrl - loml 593h vcat.rslsr(2) - - - - - - - - 594h - - - rsackl sql ctrl - loml 595h vcat.rslsr(3) - - - - - - - - 596h - - - rsackl sql ctrl - loml 597h vcat.rslsr(4) - - - - - - - - 598h - - - rsackl sql ctrl - loml 599h vcat.rslsr(5) - - - - - - - - 59ah - - - rsackl sql ctrl - loml 59bh vcat.rslsr(6) - - - - - - - - 59ch - - - rsackl sql ctrl - loml 59dh vcat.rslsr(7) - - - - - - - - 59eh - - - rsackl sql ctrl - loml 59fh vcat.rslsr(8) - - - - - - - - 5a0h - - - rsackl sql ctrl - loml 5a1h vcat.rslsr(9) - - - - - - - - 5a2h - - - rsackl sql ctrl - loml 5a3h vcat.rslsr(10) - - - - - - - - 5a4h - - - rsackl sql ctrl - loml 5a5h vcat.rslsr(11) - - - - - - - - 5a6h - - - rsackl sql ctrl - loml 5a7h vcat.rslsr(12) - - - - - - - - 5a8h - - - rsackl sql ctrl - loml 5a9h vcat.rslsr(13) - - - - - - - - 5aah - - - rsackl sql ctrl - loml 5abh vcat.rslsr(14) - - - - - - - - 5ach - - - rsackl sql ctrl - loml 5adh vcat.rslsr(15) - - - - - - - - 5aeh - - - rsackl sql ctrl - loml 5afh vcat.rslsr(16) - - - - - - - - 5b0h - - - rsackie sqie ctrie - lomie 5b1h vcat.rsie (1) - - - - - - - - 5b2h - - - rsackie sqie ctrie - lomie 5b3h vcat.rsie (2) - - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 127 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 5b4h - - - rsackie sqie ctrie - lomie 5b5h vcat.rsie (3) - - - - - - - - 5b6h - - - rsackie sqie ctrie - lomie 5b7h vcat.rsie (4) - - - - - - - - 5b8h - - - rsackie sqie ctrie - lomie 5b9h vcat.rsie (5) - - - - - - - - 5bah - - - rsackie sqie ctrie - lomie 5bbh vcat.rsie (6) - - - - - - - - 5bch - - - rsackie sqie ctrie - lomie 5bdh vcat.rsie (7) - - - - - - - - 5beh - - - rsackie sqie ctrie - lomie 5bfh vcat.rsie (8) - - - - - - - - 5c0h - - - rsackie sqie ctrie - lomie 5c1h vcat.rsie (9) - - - - - - - - 5c2h - - - rsackie sqie ctrie - lomie 5c3h vcat.rsie (10) - - - - - - - - 5c4h - - - rsackie sqie ctrie - lomie 5c5h vcat.rsie (11) - - - - - - - - 5c6h - - - rsackie sqie ctrie - lomie 5c7h vcat.rsie (12) - - - - - - - - 5c8h - - - rsackie sqie ctrie - lomie 5c9h vcat.rsie (13) - - - - - - - - 5cah - - - rsackie sqie ctrie - lomie 5cbh vcat.rsie (14) - - - - - - - - 5cch - - - rsackie sqie ctrie - lomie 5cdh vcat.rsie (15) - - - - - - - - 5ceh - - - rsackie sqie ctrie - lomie 5cfh vcat.rsie (16) - - - - - - - - 5d0h rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5d1h vcat.rsr3 (1) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5d2h rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5d3h vcat.rsr3 (2) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5d4h rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5d5h vcat.rsr3 (3) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5d6h rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5d7h vcat.rsr3 (4) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5d8h rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5d9h vcat.rsr3 (5) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5dah rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5dbh vcat.rsr3 (6) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5dch vcat.rsr3 (7) rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 128 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 5ddh rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5deh rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5dfh vcat.rsr3 (8) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5e0h rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5e1h vcat.rsr3 (9) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5e2h rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5e3h vcat.rsr3 (10) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5e4h rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5e5h vcat.rsr3 (11) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5e6h rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5e7h vcat.rsr3 (12) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5e8h rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5e9h vcat.rsr3 (13) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5eah rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5ebh vcat.rsr3 (14) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5ech rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5edh vcat.rsr3 (15) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 5eeh rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 5efh vcat.rsr3 (16) rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 serial interface global 600h llb8 llb7 llb6 llb5 llb4 llb3 llb2 llb1 601h li.lcr1 llb16 llb15 llb14 llb13 llb12 llb11 llb10 llb9 602h tlb8 tlb7 tlb6 tlb5 tlb4 tlb3 tlb2 tlb1 603h li.lcr2 tlb16 tlb15 tlb14 tlb13 tlb12 tlb11 tlb10 tlb9 604h tclka8 tclka7 tclka6 tclka5 tclka4 tclka3 tclka2 tclka1 605h li.tcsr - - - tmclka4 - - - tmclka3 606h - - - - - - - tvclka1 607h li.tvcsr - - - - - - - - 608h rclka8 rclka7 rclka6 rclka5 rclka4 rclka3 rclka2 rclka1 609h li.rcsr rclka16 rclka15 rclka14 rclka13 rclka12 rclka11 rclka10 rclka9 60ah - - - - - - - rvclka1 60bh li.rvcsr - - - - - - - - transmit serial per-port 640h - - - tclkinv - ts_setup1 ts_setup0 td_sel 641h li.tcr (1) - - - - - - - - 648h - - - tclkinv - ts_setup1 ts_setup0 td_sel 649h li.tcr (2) - - - - - - - - 650h - - - tclkinv - ts_setup1 ts_setup0 td_sel 651h li.tcr (3) - - - - - - - - 658h - - - tclkinv - ts_setup1 ts_setup0 td_sel 659h li.tcr (4) - - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 129 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 660h - - - tclkinv - ts_setup1 ts_setup0 td_sel 661h li.tcr (5) - - - - - - - - 668h - - - tclkinv - ts_setup1 ts_setup0 td_sel 669h li.tcr (6) - - - - - - - - 670h - - - tclkinv - ts_setup1 ts_setup0 td_sel 671h li.tcr (7) - - - - - - - - 678h - - - tclkinv - ts_setup1 ts_setup0 td_sel 679h li.tcr (8) - - - - - - - - 680h - - - tclkinv - ts_setup1 ts_setup0 - 681h li.tcr (9) - - - - - - - - 688h - - - tclkinv - ts_setup1 ts_setup0 - 689h li.tcr (10) - - - - - - - - 690h - - - tclkinv - ts_setup1 ts_setup0 - 691h li.tcr (11) - - - - - - - - 698h - - - tclkinv - ts_setup1 ts_setup0 - 699h li.tcr (12) - - - - - - - - 6a0h - - - tclkinv - ts_setup1 ts_setup0 - 6a1h li.tcr (13) - - - - - - - - 6a8h - - - tclkinv - ts_setup1 ts_setup0 - 6a9h li.tcr (14) - - - - - - - - 6b0h - - - tclkinv - ts_setup1 ts_setup0 - 6b1h li.tcr (15) - - - - - - - - 6b8h - - - tclkinv - ts_setup1 ts_setup0 - 6b9h li.tcr (16) - - - - - - - - 6c0h tvopf4 tvopf3 tvopf2 tvopf1 tvopf0 tsyncc pc tpe 6c1h li.tvpcr - - - - - - tvfrst tvclki 6c2h - - - - - - tvfu tvfo 6c3h li.tvfsr - - - - - - - - 6c4h - - - - - - tvful tvfol 6c5h li.tvflsr - - - - - - - - 6c6h - - - - - - tvfulie tvfolie 6c7h li.tvfsrie - - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 130 of 375 a ddr name b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 receive serial per-port 740h - - - rclkinv - - rfrst - 741h li.rcr1 (1) - - - - - - - - 748h - - - rclkinv - - rfrst - 749h li.rcr1 (2) - - - - - - - - 750h - - - rclkinv - - rfrst - 751h li.rcr1 (3) - - - - - - - - 758h - - - rclkinv - - rfrst - 759h li.rcr1 (4) - - - - - - - - 760h - - - rclkinv - - rfrst - 761h li.rcr1 (5) - - - - - - - - 768h - - - rclkinv - - rfrst - 769h li.rcr1 (6) - - - - - - - - 770h - - - rclkinv - - rfrst - 771h li.rcr1 (7) - - - - - - - - 778h - - - rclkinv - - rfrst - 779h li.rcr1 (8) - - - - - - - - 780h - - - rclkinv - - rfrst - 781h li.rcr1 (9) - - - - - - - - 788h - - - rclkinv - - rfrst - 789h li.rcr1 (10) - - - - - - - - 790h - - - rclkinv - - rfrst - 791h li.rcr1 (11) - - - - - - - - 798h - - - rclkinv - - rfrst - 799h li.rcr1 (12) - - - - - - - - 7a0h - - - rclkinv - - rfrst - 7a1h li.rcr1 (13) - - - - - - - - 7a8h - - - rclkinv - - rfrst - 7a9h li.rcr1 (14) - - - - - - - - 7b0h - - - rclkinv - - rfrst - 7b1h li.rcr1 (15) - - - - - - - - 7b8h - - - rclkinv - - rfrst - 7b9h li.rcr1 (16) - - - - - - - - 7c0h rvopf4 rvopf3 rvopf2 rvopf1 rvopf0 rsyncc pc rpe 7c1h li.rvpcr - - - - - - rvfrst rvclki
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 131 of 375 10.1.2 mac indirect register bit map table 10-3. mac indirect register bit map a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 0000h su.maccr 31:24 reserved reserved reserved reserved reserved reserved reserved reserved 23:16 wdd jd fbe jfe reserved reserved reserved reserved 15:8 gmiimiis em dro lm dm reserved drty apst 7:0 acst bolmt1 bolmt0 dc te re reserved reserved 0004h su.macffr 31:24 raf reserved reserved reserved reserved reserved reserved reserved 23:16 reserved reserved reserved reserved reserved reserved reserved reserved 15:8 reserved reserved reserved reserved reserved reserved reserved reserved 7:0 pcf reserved dbf pam invf hfuf hfmf pm 0008h su.machthr 31:24 hth[31] hth[30] hth[29] hth[28] hth[27] hth[26] hth[25] hth[24] 23:16 hth[23] hth[22] hth[21] hth[20] hth[19] hth[18] hth[17] hth[16] 15:8 hth[15] hth[14] hth[13] hth[12] hth[11] hth[10] hth[9] hth[8] 7:0 hth[7] hth[6] hth[5] hth[4] hth[3] hth[ 2] hth[1] hth[0] 000ch su.machtlr 31:24 htl[31] htl[30] htl[29] htl[28] htl[27] htl[26] htl[25] htl[24] 23:16 htl[23] htl[22] htl[21] htl[20] htl[19] htl[18] htl[17] htl[16] 15:8 htl[15] htl[14] htl[13] htl[12] htl[11] htl[10] htl[9] htl[8] 7:0 htl[7] htl[6] htl[5] htl[4] htl[3] htl[2] htl[1] htl[0] 0010h su.gmiia 31:24 reserved reserved reserved reserved reserved reserved reserved reserved 23:16 reserved reserved reserved reserved reserved reserved reserved reserved 15:8 ppa[4] ppa[3] ppa[2] ppa[1] ppa[0] gm[4] gm[3] gm[2] 7:0 gm[1] gm[0] reserved reserved cr[1] cr[0] gw gb 0014h su.gmiid 31:24 reserved reserved reserved reserved reserved reserved reserved reserved 23:16 reserved reserved reserved reserved reserved reserved reserved reserved 15:8 gd[15] gd[14] gd[13] gd[12] gd[11] gd[10] gd[9] gd[8] 7:0 gd[7] gd[6] gd[5] gd[4] gd[3] gd[2] gd[1] gd[0] 0018h su.macfcr 31:24 pt[15] pt[14] pt[13] pt[12] pt[11] pt[10] pt[9] pt[8] 23:16 pt[7] pt[6] pt[5] pt[4] pt[3] pt[2] pt[1] pt[0] 15:8 reserved reserved reserved reserved reserved reserved reserved reserved 7:0 reserved reserved reserved plt up rfe tfe fcb 001ch su.vlantr 31:24 - - - - - - - - 23:16 - - - - - - - - 15:8 vltid[15] vltid[14] vltid[13] vltid[12] vltid[11] vltid[10] vltid[9] vltid[8] 7:0 vltid[7] vltid[6] vltid[5] vltid[4] vltid[3] vltid[2] vltid[1] vltid[0] 0040h su.addr0h 31:24 maddr0ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr0[47] maddr0[46] maddr0[45] maddr0[44] maddr0[43] maddr0[42] maddr0[41] maddr0[40] 7:0 maddr0[39] maddr0[38] maddr0[37] maddr0[36] maddr0[35] maddr0[34] maddr0[33] maddr0[32] 0044h su.addr0l 31:24 maddr0[31] maddr0[30] maddr0[29] maddr0[28] maddr0[27] maddr0[26] maddr0[25] maddr0[24] 23:16 maddr0[23] maddr0[22] maddr0[21] maddr0[20] maddr0[19] maddr0[18] maddr0[17] maddr0[16] 15:8 maddr0[15] maddr0[14] maddr0[13] maddr0[12] maddr0[11] maddr0[10] maddr0[9] maddr0[8] 7:0 maddr0[7] maddr0[6] maddr0[5] maddr0[4] maddr0[3] maddr0[2] maddr0[1] maddr0[0]
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 132 of 375 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 0048h su.addr1h 31:24 maddr1ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr1[47] maddr1[46] maddr1[45] maddr1[44] maddr1[43] maddr1[42] maddr1[41] maddr1[40] 7:0 maddr1[39] maddr1[38] maddr1[37] maddr1[36] maddr1[35] maddr1[34] maddr1[33] maddr1[32] 004ch su.addr1l 31:24 maddr1[31] maddr1[30] maddr1[29] maddr1[28] maddr1[27] maddr1[26] maddr1[25] maddr1[24] 23:16 maddr1[23] maddr1[22] maddr1[21] maddr1[20] maddr1[19] maddr1[18] maddr1[17] maddr1[16] 15:8 maddr1[15] maddr1[14] maddr1[13] maddr1[12] maddr1[11] maddr1[10] maddr1[9] maddr1[8] 7:0 maddr1[7] maddr1[6] maddr1[5] maddr1[4] maddr1[3] maddr1[2] maddr1[1] maddr1[0] 0050h su.addr2h 31:24 maddr2ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr2[47] maddr2[46] maddr2[45] maddr2[44] maddr2[43] maddr2[42] maddr2[41] maddr2[40] 7:0 maddr2[39] maddr2[38] maddr2[37] maddr2[36] maddr2[35] maddr2[34] maddr2[33] maddr2[32] 0054h su.addr2l 31:24 maddr2[31] maddr2[30] maddr2[29] maddr2[28] maddr2[27] maddr2[26] maddr2[25] maddr2[24] 23:16 maddr2[23] maddr2[22] maddr2[21] maddr2[20] maddr2[19] maddr2[18] maddr2[17] maddr2[16] 15:8 maddr2[15] maddr2[14] maddr2[13] maddr2[12] maddr2[11] maddr2[10] maddr2[9] maddr2[8] 7:0 maddr2[7] maddr2[6] maddr2[5] maddr2[4] maddr2[3] maddr2[2] maddr2[1] maddr2[0] 0058h su.addr3h 31:24 maddr3ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr3[47] maddr3[46] maddr3[45] maddr3[44] maddr3[43] maddr3[42] maddr3[41] maddr3[40] 7:0 maddr3[39] maddr3[38] maddr3[37] maddr3[36] maddr3[35] maddr3[34] maddr3[33] maddr3[32] 005ch su.addr3l 31:24 maddr3[31] maddr3[30] maddr3[29] maddr3[28] maddr3[27] maddr3[26] maddr3[25] maddr3[24] 23:16 maddr3[23] maddr3[22] maddr3[21] maddr3[20] maddr3[19] maddr3[18] maddr3[17] maddr3[16] 15:8 maddr3[15] maddr3[14] maddr3[13] maddr3[12] maddr3[11] maddr3[10] maddr3[9] maddr3[8] 7:0 maddr3[7] maddr3[6] maddr3[5] maddr3[4] maddr3[3] maddr3[2] maddr3[1] maddr3[0] 0060h su.addr4h 31:24 maddr4ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr4[47] maddr4[46] maddr4[45] maddr4[44] maddr4[43] maddr4[42] maddr4[41] maddr4[40] 7:0 maddr4[39] maddr4[38] maddr4[37] maddr4[36] maddr4[35] maddr4[34] maddr4[33] maddr4[32] 0064h su.addr4l 31:24 maddr4[31] maddr4[30] maddr4[29] maddr4[28] maddr4[27] maddr4[26] maddr4[25] maddr4[24] 23:16 maddr4[23] maddr4[22] maddr4[21] maddr4[20] maddr4[19] maddr4[18] maddr4[17] maddr4[16] 15:8 maddr4[15] maddr4[14] maddr4[13] maddr4[12] maddr4[11] maddr4[10] maddr4[9] maddr4[8] 7:0 maddr4[7] maddr4[6] maddr4[5] maddr4[4] maddr4[3] maddr4[2] maddr4[1] maddr4[0] 0068h su.addr5h 31:24 maddr5ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr5[47] maddr5[46] maddr5[45] maddr5[44] maddr5[43] maddr5[42] maddr5[41] maddr5[40] 7:0 maddr5[39] maddr5[38] maddr5[37] maddr5[36] maddr5[35] maddr5[34] maddr5[33] maddr5[32] 006ch su.addr5l 31:24 maddr5[31] maddr5[30] maddr5[29] maddr5[28] maddr5[27] maddr5[26] maddr5[25] maddr5[24] 23:16 maddr5[23] maddr5[22] maddr5[21] maddr5[20] maddr5[19] maddr5[18] maddr5[17] maddr5[16] 15:8 maddr5[15] maddr5[14] maddr5[13] maddr5[12] maddr5[11] maddr5[10] maddr5[9] maddr5[8] 7:0 maddr5[7] maddr5[6] maddr5[5] maddr5[4] maddr5[3] maddr5[2] maddr5[1] maddr5[0] 0070h su.addr6h 31:24 maddr6ae - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 133 of 375 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 23:16 - - - - - - - - 15:8 maddr6[47] maddr6[46] maddr6[45] maddr6[44] maddr6[43] maddr6[42] maddr6[41] maddr6[40] 7:0 maddr6[39] maddr6[38] maddr6[37] maddr6[36] maddr6[35] maddr6[34] maddr6[33] maddr6[32] 0074h su.addr6l 31:24 maddr6[31] maddr6[30] maddr6[29] maddr6[28] maddr6[27] maddr6[26] maddr6[25] maddr6[24] 23:16 maddr6[23] maddr6[22] maddr6[21] maddr6[20] maddr6[19] maddr6[18] maddr6[17] maddr6[16] 15:8 maddr6[15] maddr6[14] maddr6[13] maddr6[12] maddr6[11] maddr6[10] maddr6[9] maddr6[8] 7:0 maddr6[7] maddr6[6] maddr6[5] maddr6[4] maddr6[3] maddr6[2] maddr6[1] maddr6[0] 0078h su.addr7h 31:24 maddr7ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr7[47] maddr7[46] maddr7[45] maddr7[44] maddr7[43] maddr7[42] maddr7[41] maddr7[40] 7:0 maddr7[39] maddr7[38] maddr7[37] maddr7[36] maddr7[35] maddr7[34] maddr7[33] maddr7[32] 007ch su.addr7l 31:24 maddr7[31] maddr7[30] maddr7[29] maddr7[28] maddr7[27] maddr7[26] maddr7[25] maddr7[24] 23:16 maddr7[23] maddr7[22] maddr7[21] maddr7[20] maddr7[19] maddr7[18] maddr7[17] maddr7[16] 15:8 maddr7[15] maddr7[14] maddr7[13] maddr7[12] maddr7[11] maddr7[10] maddr7[9] maddr7[8] 7:0 maddr7[7] maddr7[6] maddr7[5] maddr7[4] maddr7[3] maddr7[2] maddr7[1] maddr7[0] 0080h su.addr8h 31:24 maddr8ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr8[47] maddr8[46] maddr8[45] maddr8[44] maddr8[43] maddr8[42] maddr8[41] maddr8[40] 7:0 maddr8[39] maddr8[38] maddr8[37] maddr8[36] maddr8[35] maddr8[34] maddr8[33] maddr8[32] 0084h su.addr8l 31:24 maddr8[31] maddr8[30] maddr8[29] maddr8[28] maddr8[27] maddr8[26] maddr8[25] maddr8[24] 23:16 maddr8[23] maddr8[22] maddr8[21] maddr8[20] maddr8[19] maddr8[18] maddr8[17] maddr8[16] 15:8 maddr8[15] maddr8[14] maddr8[13] maddr8[12] maddr8[11] maddr8[10] maddr8[9] maddr8[8] 7:0 maddr8[7] maddr8[6] maddr8[5] maddr8[4] maddr8[3] maddr8[2] maddr8[1] maddr8[0] 0088h su.addr9h 31:24 maddr9ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr9[47] maddr9[46] maddr9[45] maddr9[44] maddr9[43] maddr9[42] maddr9[41] maddr9[40] 7:0 maddr9[39] maddr9[38] maddr9[37] maddr9[36] maddr9[35] maddr9[34] maddr9[33] maddr9[32] 008ch su.addr9l 31:24 maddr9[31] maddr9[30] maddr9[29] maddr9[28] maddr9[27] maddr9[26] maddr9[25] maddr9[24] 23:16 maddr9[23] maddr9[22] maddr9[21] maddr9[20] maddr9[19] maddr9[18] maddr9[17] maddr9[16] 15:8 maddr9[15] maddr9[14] maddr9[13] maddr9[12] maddr9[11] maddr9[10] maddr9[9] maddr9[8] 7:0 maddr9[7] maddr9[6] maddr9[5] maddr9[4] maddr9[3] maddr9[2] maddr9[1] maddr9[0] 0090h su.addr10h 31:24 maddr10ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr10[47] maddr10[46] maddr10[45] maddr10[44] ma ddr10[43] maddr10[42] ma ddr10[41] maddr10[40] 7:0 maddr10[39] maddr10[38] maddr10[37] maddr10[36] ma ddr10[35] maddr10[34] ma ddr10[33] maddr10[32] 0094h su.addr10l 31:24 maddr10[31] maddr10[30] maddr10[29] maddr10[28] ma ddr10[27] maddr10[26] ma ddr10[25] maddr10[24] 23:16 maddr10[23] maddr10[22] maddr10[21] maddr10[20] ma ddr10[19] maddr10[18] ma ddr10[17] maddr10[16] 15:8 maddr10[15] maddr10[14] maddr10[13] maddr10[12] ma ddr10[11] maddr10[10] ma ddr10[9] ma ddr10[8] 7:0 maddr10[7] maddr10[ 6] maddr10[5] ma ddr10[4] maddr10[3] maddr10[2] maddr 10[1] maddr10[0] 0098h su.addr11h 31:24 maddr11ae - - - - - - - 23:16 - - - - - - - -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 134 of 375 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 15:8 maddr11[47] maddr11[46] maddr11[45] maddr11[44] ma ddr11[43] maddr11[42] ma ddr11[41] maddr11[40] 7:0 maddr11[39] maddr11[38] maddr11[37] maddr11[36] ma ddr11[35] maddr11[34] ma ddr11[33] maddr11[32] 009ch su.addr11l 31:24 maddr11[31] maddr11[30] maddr11[29] maddr11[28] ma ddr11[27] maddr11[26] ma ddr11[25] maddr11[24] 23:16 maddr11[23] maddr11[22] maddr11[21] maddr11[20] ma ddr11[19] maddr11[18] ma ddr11[17] maddr11[16] 15:8 maddr11[15] maddr11[14] maddr11[13] maddr11[12] ma ddr11[11] maddr11[10] ma ddr11[9] ma ddr11[8] 7:0 maddr11[7] maddr11[ 6] maddr11[5] ma ddr11[4] maddr11[3] maddr11[2] maddr 11[1] maddr11[0] 00a0h su.addr12h 31:24 maddr12ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr12[47] maddr12[46] maddr12[45] maddr12[44] ma ddr12[43] maddr12[42] ma ddr12[41] maddr12[40] 7:0 maddr12[39] maddr12[38] maddr12[37] maddr12[36] ma ddr12[35] maddr12[34] ma ddr12[33] maddr12[32] 00a4h su.addr12l 31:24 maddr12[31] maddr12[30] maddr12[29] maddr12[28] ma ddr12[27] maddr12[26] ma ddr12[25] maddr12[24] 23:16 maddr12[23] maddr12[22] maddr12[21] maddr12[20] ma ddr12[19] maddr12[18] ma ddr12[17] maddr12[16] 15:8 maddr12[15] maddr12[14] maddr12[13] maddr12[12] ma ddr12[11] maddr12[10] ma ddr12[9] ma ddr12[8] 7:0 maddr12[7] maddr12[ 6] maddr12[5] ma ddr12[4] maddr12[3] maddr12[2] maddr 12[1] maddr12[0] 00a8h su.addr13h 31:24 maddr13ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr13[47] maddr13[46] maddr13[45] maddr13[44] ma ddr13[43] maddr13[42] ma ddr13[41] maddr13[40] 7:0 maddr13[39] maddr13[38] maddr13[37] maddr13[36] ma ddr13[35] maddr13[34] ma ddr13[33] maddr13[32] 00ach su.addr13l 31:24 maddr13[31] maddr13[30] maddr13[29] maddr13[28] ma ddr13[27] maddr13[26] ma ddr13[25] maddr13[24] 23:16 maddr13[23] maddr13[22] maddr13[21] maddr13[20] ma ddr13[19] maddr13[18] ma ddr13[17] maddr13[16] 15:8 maddr13[15] maddr13[14] maddr13[13] maddr13[12] ma ddr13[11] maddr13[10] ma ddr13[9] ma ddr13[8] 7:0 maddr13[7] maddr13[ 6] maddr13[5] ma ddr13[4] maddr13[3] maddr13[2] maddr 13[1] maddr13[0] 00b0h su.addr14h 31:24 maddr14ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr14[47] maddr14[46] maddr14[45] maddr14[44] ma ddr14[43] maddr14[42] ma ddr14[41] maddr14[40] 7:0 maddr14[39] maddr14[38] maddr14[37] maddr14[36] ma ddr14[35] maddr14[34] ma ddr14[33] maddr14[32] 00b4h su.addr14l 31:24 maddr14[31] maddr14[30] maddr14[29] maddr14[28] ma ddr14[27] maddr14[26] ma ddr14[25] maddr14[24] 23:16 maddr14[23] maddr14[22] maddr14[21] maddr14[20] ma ddr14[19] maddr14[18] ma ddr14[17] maddr14[16] 15:8 maddr14[15] maddr14[14] maddr14[13] maddr14[12] ma ddr14[11] maddr14[10] ma ddr14[9] ma ddr14[8] 7:0 maddr14[7] maddr14[ 6] maddr14[5] ma ddr14[4] maddr14[3] maddr14[2] maddr 14[1] maddr14[0] 00b8h su.addr15h 31:24 maddr15ae - - - - - - - 23:16 - - - - - - - - 15:8 maddr15[47] maddr15[46] maddr15[45] maddr15[44] ma ddr15[43] maddr15[42] ma ddr15[41] maddr15[40] 7:0 maddr15[39] maddr15[38] maddr15[37] maddr15[36] ma ddr15[35] maddr15[34] ma ddr15[33] maddr15[32] 00bch su.addr15l 31:24 maddr15[31] maddr15[30] maddr15[29] maddr15[28] ma ddr15[27] maddr15[26] ma ddr15[25] maddr15[24] 23:16 maddr15[23] maddr15[22] maddr15[21] maddr15[20] ma ddr15[19] maddr15[18] ma ddr15[17] maddr15[16] 15:8 maddr15[15] maddr15[14] maddr15[13] maddr15[12] ma ddr15[11] maddr15[10] ma ddr15[9] ma ddr15[8] 7:0 maddr15[7] maddr15[ 6] maddr15[5] ma ddr15[4] maddr15[3] maddr15[2] maddr 15[1] maddr15[0] 00c0h su.pcscr 31:24 - - - - - - - - 23:16 - - - - - - lr ecd 15:8 - ele ane - - - ran -
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 135 of 375 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 7:0 - - - - - - - - 00c4h su.ansr 31:24 - - - - - - - - 23:16 - - - - - - - - 15:8 - - - - - - - es 7:0 - - anc - ana ls - - 00d8h su.lsr 31:24 - - - - - - - - 23:16 - - - - - - - - 15:8 - - - - - - - - 7:0 - - - - linkup lnkspd[1] lnkspd[0] linkm 0100h su.mmcctrl 31:24 - - - - - - - - 23:16 - - - - - - - - 15:8 - - - - - - - - 7:0 - - - - - ror csr crst 0104h su.mmcrsr 31:24 - - - - - - - - 23:16 rxwdog rxvlan rxovfl rxpause rxrange rxlnerr rxucast rx1k_max 15:8 rx512_1k rx256_511 rx128_255 rx65_127 rx0_64 rxovrsz rxunrsz rxjbbr 7:0 rxrunt rxalgn rxcrc rxmfc rxgbfc rxbcg rxbcgb rxfc 0108h su.mmctsr 31:24 - - - - - - - txvlan 23:16 txpause txxcsvdf txfcnt txbcnt txcerr txxcsvcl txltcl txdfrd 15:8 txmlticl txsnglcl txufe txbfc txmfc txucast tx1k_max tx512_1k 7:0 tx256_511 tx128_255 tx65_127 tx0_64 txgmfc txgbfc txfc txbc 010ch su.mmcrim 31:24 - - - - - - - - 23:16 rxwdog rxvlan rxovfl rxpause rxrange rxlnerr rxucast rx1k_max 15:8 rx512_1k rx256_511 rx128_255 rx65_127 rx0_64 rxovrsz rxunrsz rxjbbr 7:0 rxrunt rxalgn rxcrc rxmfc rxgbfc rxbcg rxbcgb rxfc 0110h su.mmctim 31:24 - - - - - - - txvlan 23:16 txpause txxcsvdf txfcnt txbcnt txcerr txxcsvcl txltcl txdfrd 15:8 txmlticl txsnglcl txufe txbfc txmfc txucast tx1k_max tx512_1k 7:0 tx256_511 tx128_255 tx65_127 tx0_64 txgmfc txgbfc txfc txbc 0114h su.txbc 31:24 txbc[31] txbc[30] txbc[29] txbc[28] txbc[27] txbc[26] txbc[25] txbc[24] 23:16 txbc[23] txbc[22] txbc[21] txbc[20] txbc[19] txbc[18] txbc[17] txbc[16] 15:8 txbc[15] txbc[14] txbc[13] txbc[12] txbc[11] txbc[10] txbc[9] txbc[8] 7:0 txbc[7] txbc[6] txbc[5 ] txbc[4] txbc[3] txbc [2] txbc[1] txbc[0] 0118h su.txfc 31:24 txfc[31] txfc[30] txfc[29] txfc[28] txfc[27] txfc [26] txfc[25] txfc[24] 23:16 txfc[23] txfc[22] txfc[21] txfc[20] txfc[19] txfc [18] txfc[17] txfc[16] 15:8 txfc[15] txfc[14] txfc[ 13] txfc[12] txfc[11] tx fc[10] txfc[9] txfc[8] 7:0 txfc[7] txfc[6] txfc[5] txfc[4] txfc[3] txfc[2] txfc[1] txfc[0] 011ch su.txgbfc 31:24 txgbfc[31] txgbfc[30] txgbfc[ 29] txgbfc[28] txgbfc[27] txgbfc [26] txgbfc[25] txgbfc[24] 23:16 txgbfc[23] txgbfc[22] txgbfc[ 21] txgbfc[20] txgbfc[19] txgbfc [18] txgbfc[17] txgbfc[16]
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 136 of 375 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 15:8 txgbfc[15] txgbfc[14] txgbfc [13] txgbfc[12] txgbfc[11] txgb fc[10] txgbfc[9] txgbfc[8] 7:0 txgbfc[7] txgbfc[6] txgbfc[5] txgbfc[4] tx gbfc[3] txgbfc[2] txgbfc[1] txgbfc[0] 0120h su.txgmfc 31:24 txgmfc[31] txgmfc[30] txgmfc[29] txgmfc[28] txgmfc[27] txgmfc[26] txgmfc[25] txgmfc[24] 23:16 txgmfc[23] txgmfc[22] txgmfc[21] txgmfc[20] txgmfc[19] txgmfc[18] txgmfc[17] txgmfc[16] 15:8 txgmfc[15] txgmfc[14] txgmfc[13] txgmfc[12] txgmfc[11] txgmfc[10] txgmfc[9] txgmfc[8] 7:0 txgmfc[7] txgmfc[6] txgmfc[5] txgmfc[4] tx gmfc[3] txgmfc[2] txgmfc[1] txgmfc[0] 0124h su.tx0_64 31:24 tx0_64[31] tx0_64[30] tx0_64[29] tx0_64[28] tx0_64[27] tx0_64[26] tx0_64[25] tx0_64[24] 23:16 tx0_64[23] tx0_64[22] tx0_64[21] tx0_64[20] tx0_64[19] tx0_64[18] tx0_64[17] tx0_64[16] 15:8 tx0_64[15] tx0_64[14] tx0_64[13] tx0_64[12] tx 0_64[11] tx0_64[10] tx0_64[9] tx0_64[8] 7:0 tx0_64[7] tx0_64[6] tx0_64[5] tx0_64[4] tx0_64[3] tx0_64[2] tx0_64[1] tx0_64[0] 0128h su.tx65_127 31:24 tx65_127[31] tx65_127[30] tx65_127[29] tx65_127[28] t x65_127[27] tx65_127[26] tx65_127[25] tx65_127[24] 23:16 tx65_127[23] tx65_127[22] tx65_127[21] tx65_127[20] t x65_127[19] tx65_127[18] tx65_127[17] tx65_127[16] 15:8 tx65_127[15] tx65_127[14] tx65_127[13] tx65_127[12] t x65_127[11] tx65_127[10] tx65_127[9] tx65_127[8] 7:0 tx65_127[7] tx65_127[6] tx65_127[5] tx65_127[4] tx65_127[3] tx65_127[2] tx65_127[1] tx65_127[0] 012ch su.tx128_255 31:24 tx128_255[31] tx128_255[30] tx128_255[29] tx128_255[28] tx128_255[27] tx128_255[26] tx128_255[25] tx128_255[24] 23:16 tx128_255[23] tx128_255[22] tx128_255[21] tx128_255[20] tx128_255[19] tx128_255[18] tx128_255[17] tx128_255[16] 15:8 tx128_255[15] tx128_255[14] tx128_255[13] tx128_255[12] tx128_255[11] tx128_255[10] tx128_255[9] tx128_255[8] 7:0 tx128_255[7] tx128_255[6] tx128_255[5] tx128_255[4] tx128_255[3] tx128_255[2] tx128_255[1] tx128_255[0] 0130h su.tx256_511 31:24 tx256_511[31] tx256_511[30] tx256_511[29] tx256_511[28] tx256_511[27] tx256_511[26] tx256_511[25] tx256_511[24] 23:16 tx256_511[23] tx256_511[22] tx256_511[21] tx256_511[20] tx256_511[19] tx256_511[18] tx256_511[17] tx256_511[16] 15:8 tx256_511[15] tx256_511[14] tx256_511[13] tx256_511[12] tx256_511[11] tx256_511[10] tx256_511[9] tx256_511[8] 7:0 tx256_511[7] tx256_511[6] tx256_511[5] tx256_511[4] tx256_511[3] tx256_511[2] tx256_511[1] tx256_511[0] 0134h su.tx512_1k 31:24 tx512_1k[31] tx512_1k[30] tx512_1k[29] tx512_1k[28] tx512_1k[27] tx512_1k[26] tx512_1k[25] tx512_1k[24] 23:16 tx512_1k[23] tx512_1k[22] tx512_1k[21] tx512_1k[20] tx512_1k[19] tx512_1k[18] tx512_1k[17] tx512_1k[16] 15:8 tx512_1k[15] tx512_1k[14] tx512_1k[13] tx512_1k[12] tx512_1k[11] tx512_1k[10] tx512_1k[9] tx512_1k[8] 7:0 tx512_1k[7] tx512_1k[6] tx512_1k[5] tx512_1k[4] tx512_1k[3] tx512_1k[2] tx512_1k[1] tx512_1k[0] 0138h su.tx1k_max 31:24 tx1k_max[31] tx1k_max[30] tx1k_max[29] tx1k_max[28] tx1k_max[27] tx1k_max[26] tx1k_max[25] tx1k_max[24] 23:16 tx1k_max[23] tx1k_max[22] tx1k_max[21] tx1k_max[20] tx1k_max[19] tx1k_max[18] tx1k_max[17] tx1k_max[16] 15:8 tx1k_max[15] tx1k_max[14] tx1k_max[13] tx1k_max[12] tx1k_max[11] tx1k_max[10] tx1k_max[9] tx1k_max[8] 7:0 tx1k_max[7] tx1k_max[6] tx1k_max[5] tx1k_max[4] tx1k_max[3] tx1k_max[2] tx1k_max[1] tx1k_max[0] 013ch su.txucast 31:24 txucast[31] txucast[30] txucast[29] txucast[28] tx ucast[27] txucast[26] txucast[25] txucast[24] 23:16 txucast[23] txucast[22] txucast[21] txucast[20] tx ucast[19] txucast[18] txucast[17] txucast[16] 15:8 txucast[15] txucast[14] txucast[13] txucast[12] txucast[11] txucast[10] txucast[9] txucast[8] 7:0 txucast[7] txucast[6] txucast[5] txucast[4] txucast[3] txucast[2] txucast[1] txucast[0] 0140h su.txmfc 31:24 txmfc[31] txmfc[30] txmfc[29] txmfc[28] txmfc[27] txmfc[26] txmfc[25] txmfc[24] 23:16 txmfc[23] txmfc[22] txmfc[21] txmfc[20] txmfc[19] txmfc[18] txmfc[17] txmfc[16] 15:8 txmfc[15] txmfc[14] txmfc[13] txmfc[12] txmfc[11] txmfc[10] txmfc[9] txmfc[8] 7:0 txmfc[7] txmfc[6] txmfc[5] txmfc[4] txmfc[3] txmfc[2] txmfc[1] txmfc[0] 0144h su.txbfc 31:24 txbfc[31] txbfc[30] txbfc[29] txbfc[28] txbfc[27] txbfc[26] txbfc[25] txbfc[24] 23:16 txbfc[23] txbfc[22] txbfc[21] txbfc[20] txbfc[19] txbfc[18] txbfc[17] txbfc[16] 15:8 txbfc[15] txbfc[14] txbfc[13] txbfc[12] txbfc[11] txbfc[10] txbfc[9] txbfc[8] 7:0 txbfc[7] txbfc[6] txbfc[5] txbfc[4] txbfc[3] txbfc[2] txbfc[1] txbfc[0]
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 137 of 375 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 0148h su.txufe 31:24 txufe[31] txufe[30] txufe[29] txufe[28] txufe[27] txufe[26] txufe[25] txufe[24] 23:16 txufe[23] txufe[22] txufe[21] txufe[20] txufe[19] txufe[18] txufe[17] txufe[16] 15:8 txufe[15] txufe[14] txufe[13] txufe[12] txufe[11] txufe[10] txufe[9] txufe[8] 7:0 txufe[7] txufe[6] txufe[5] txufe[4] txufe[3] txufe[2] txufe[1] txufe[0] 014ch su.txsnglcl 31:24 txsnglcl[31] txsnglcl[30] txsnglcl[29] txsnglcl[28] txsnglcl[27] txsnglcl[26] txsnglcl[25] txsnglcl[24] 23:16 txsnglcl[23] txsnglcl[22] txsnglcl[21] txsnglcl[20] txsnglcl[19] txsnglcl[18] txsnglcl[17] txsnglcl[16] 15:8 txsnglcl[15] txsnglcl[14] txsnglcl[13] txsnglcl[12] txsnglcl[11] txsnglcl[10] txsnglcl[9] txsnglcl[8] 7:0 txsnglcl[7] txsnglcl[6] txsnglcl[5] txsnglcl[4] txsnglcl[3] txsnglcl[2] txsnglcl[1] txsnglcl[0] 0150h su.txmlticl 31:24 txmlticl[31] txmlticl[30] txmlticl[29] txmlticl[28] txmlticl[27] txmlticl[26] txmlticl[25] txmlticl[24] 23:16 txmlticl[23] txmlticl[22] txmlticl[21] txmlticl[20] txmlticl[19] txmlticl[18] txmlticl[17] txmlticl[16] 15:8 txmlticl[15] txmlticl[14] txmlticl[13] txmlticl[12] txmlticl[11] txmlticl[10] txmlticl[9] txmlticl[8] 7:0 txmlticl[7] txmlticl[6] txmlticl[5] txmlticl[4] txmlticl[3] txmlticl[2] txmlticl[1] txmlticl[0] 0154h su.txdfrd 31:24 txdfrd[31] txdfrd[30] txdfrd[29] txdfrd[28] txdfrd[27] txdfrd[26] txdfrd[25] txdfrd[24] 23:16 txdfrd[23] txdfrd[22] txdfrd[21] txdfrd[20] txdfrd[19] txdfrd[18] txdfrd[17] txdfrd[16] 15:8 txdfrd[15] txdfrd[14] txdfrd[13] txdfrd[12] txdfrd[11] txdfrd[10] txdfrd[9] txdfrd[8] 7:0 txdfrd[7] txdfrd[6] txdfrd[5] txdfrd[4] txdfrd[3] txdfrd[2] txdfrd[1] txdfrd[0] 0158h su.txltcl 31:24 txltcl[31] txltcl[30] txltcl[29] txltcl[28] txltcl[27] txltcl[26] txltcl[25] txltcl[24] 23:16 txltcl[23] txltcl[22] txltcl[21] txltcl[20] txltcl[19] txltcl[18] txltcl[17] txltcl[16] 15:8 txltcl[15] txltcl[14] txltcl[13] txltcl[12] txltcl[11] txltcl[10] txltcl[9] txltcl[8] 7:0 txltcl[7] txltcl[6] txltcl[5] txltcl[4] txltcl[3] txltcl[2] txltcl[1] txltcl[0] 015ch su.txxcsvcl 31:24 txxcsvcl[31] txxcsvcl[30] txxcsvcl[29] txxcsvcl[28] txxcsvcl[27] txxcsvcl[26] txxcsvcl[25] txxcsvcl[24] 23:16 txxcsvcl[23] txxcsvcl[22] txxcsvcl[21] txxcsvcl[20] txxcsvcl[19] txxcsvcl[18] txxcsvcl[17] txxcsvcl[16] 15:8 txxcsvcl[15] txxcsvcl[14] txxcsvcl[13] txxcsvcl[12] txxcsvcl[11] txxcsvcl[10] txxcsvcl[9] txxcsvcl[8] 7:0 txxcsvcl[7] txxcsvcl[6] txxcsvcl[5] txxcsvcl[4] txxcsvcl[3] txxcsvcl[2] txxcsvcl[1] txxcsvcl[0] 0160h su.txcrerr 31:24 txcrerr[31] txcrerr[30] txcrerr[29 ] txcrerr[28] txcrerr[27] txcre rr[26] txcrerr[25] txcrerr[24] 23:16 txcrerr[23] txcrerr[22] txcrerr[21 ] txcrerr[20] txcrerr[19] txcre rr[18] txcrerr[17] txcrerr[16] 15:8 txcrerr[15] txcrerr[14] txcrerr[13 ] txcrerr[12] txcrerr[11] txcrerr[10] txcrerr[9] txcrerr[8] 7:0 txcrerr[7] txcrerr[6] txcrerr[5] txcrerr[4] txcrerr[3] txcrerr[2] txcrerr[1] txcrerr[0] 0164h su.txgbc 31:24 txgbc[31] txgbc[30] txgbc[29] txgbc[28] txgbc[27] txgbc[26] txgbc[25] txgbc[24] 23:16 txgbc[23] txgbc[22] txgbc[21] txgbc[20] txgbc[19] txgbc[18] txgbc[17] txgbc[16] 15:8 txgbc[15] txgbc[14] txgbc[13] txgbc[12] txgbc[11] txgbc[10] txgbc[9] txgbc[8] 7:0 txgbc[7] txgbc[6] txgbc[5] txgbc[4] txgbc[3] txgbc[2] txgbc[1] txgbc[0] 0168h su.txgfc 31:24 txgfc[31] txgfc[30] txgfc[29] txgfc[28] txgfc[27] txgfc[26] txgfc[25] txgfc[24] 23:16 txgfc[23] txgfc[22] txgfc[21] txgfc[20] txgfc[19] txgfc[18] txgfc[17] txgfc[16] 15:8 txgfc[15] txgfc[14] txgfc[13] txgfc[12] txgfc[11] txgfc[10] txgfc[9] txgfc[8] 7:0 txgfc[7] txgfc[6] txgfc[5] txgfc[4] txgfc[3] txgfc[2] txgfc[1] txgfc[0] 016ch su.txxcsvdf 31:24 txxcsvdf[31] txxcsvdf[30] txxcsvdf[29] txxcsvdf[28] txxcsvdf[27] txxcsvdf[26] txxcsvdf[25] txxcsvdf[24] 23:16 txxcsvdf[23] txxcsvdf[22] txxcsvdf[21] txxcsvdf[20] txxcsvdf[19] txxcsvdf[18] txxcsvdf[17] txxcsvdf[16] 15:8 txxcsvdf[15] txxcsvdf[14] txxcsvdf[13] txxcsvdf[12] txxcsvdf[11] txxcsvdf[10] txxcsvdf[9] txxcsvdf[8] 7:0 txxcsvdf[7] txxcsvdf[6] txxcsvdf[5] txxcsvdf[4] txxcsvdf[3] txxcsvdf[2] txxcsvdf[1] txxcsvdf[0] 0170h su.txpause 31:24 txpause[31] txpause[30] txpause[29] txpause[28] tx pause[27] txpause[26] txpause[25] txpause[24] 23:16 txpause[23] txpause[22] txpause[21] txpause[20] tx pause[19] txpause[18] txpause[17] txpause[16]
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 138 of 375 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 15:8 txpause[15] txpause[14] txpause[13] txpause[12] txpause[11] txpause[10] txpause[9] txpause[8] 7:0 txpause[7] txpause[6] txpause[5] txpause[4] txpause[3] txpause[2] txpause[1] txpause[0] 0174h su.txvlanf 31:24 txvlanf[31] txvlanf[30] txvlanf[29] txvlanf[28] txvlanf[27] txvlanf[26] txvlanf[25] txvlanf[24] 23:16 txvlanf[23] txvlanf[22] txvlanf[21] txvlanf[20] txvlanf[19] txvlanf[18] txvlanf[17] txvlanf[16] 15:8 txvlanf[15] txvlanf[14] txvlanf[13] txvlanf[12] tx vlanf[11] txvlanf[10] tx vlanf[9] txvlanf[8] 7:0 txvlanf[7] txvlanf[6] txvlanf[ 5] txvlanf[4] txvlanf[3] txvl anf[2] txvlanf[1] txvlanf[0] 0178h reserved 31:24 - - - - - - - - 23:16 - - - - - - - - 15:8 - - - - - - - - 7:0 - - - - - - - - 017ch reserved 31:24 - - - - - - - - 23:16 - - - - - - - - 15:8 - - - - - - - - 7:0 - - - - - - - - 0180h su.rxfc 31:24 rxfc[31] rxfc[30] rxfc[29] rxfc[28] rxfc[27] rxfc [26] rxfc[25] rxfc[24] 23:16 rxfc[23] rxfc[22] rxfc[21] rxfc[20] rxfc[19] rxfc [18] rxfc[17] rxfc[16] 15:8 rxfc[15] rxfc[14] rxfc[13] rxfc[12] rxfc[11] rxfc[10] rxfc[9] rxfc[8] 7:0 rxfc[7] rxfc[6] rxfc[5] rxfc[4] rxfc[3] rxfc[2] rxfc[1] rxfc[0] 0184h su.rxbc 31:24 rxbc[31] rxbc[30] rxbc[29] rxbc[28] rxbc[27] rxbc[26] rxbc[25] rxbc[24] 23:16 rxbc[23] rxbc[22] rxbc[21] rxbc[20] rxbc[19] rxbc[18] rxbc[17] rxbc[16] 15:8 rxbc[15] rxbc[14] rxbc[13] rxbc[12] rxbc[11] rxbc[10] rxbc[9] rxbc[8] 7:0 rxbc[7] rxbc[6] rxbc[5] rxbc[4] rxbc[3] rxbc[2] rxbc[1] rxbc[0] 0188h su.rxgbc 31:24 rxgbc[31] rxgbc[30] rxgbc[29] rxgbc[28] rx gbc[27] rxgbc[26] rxgbc[25] rxgbc[24] 23:16 rxgbc[23] rxgbc[22] rxgbc[21] rxgbc[20] rx gbc[19] rxgbc[18] rxgbc[17] rxgbc[16] 15:8 rxgbc[15] rxgbc[14] rxgbc[13] rxgbc[12] rx gbc[11] rxgbc[10] rxgbc[9] rxgbc[8] 7:0 rxgbc[7] rxgbc[6] rxgbc[5] rxgbc[4] rxgbc[3] rxgbc[2] rxgbc[1] rxgbc[0] 018ch su.rxgbfc 31:24 rxgbfc[31] rxgbfc[30] rxgbfc[ 29] rxgbfc[28] rxgbfc[27] rxgb fc[26] rxgbfc[ 25] rxgbfc[24] 23:16 rxgbfc[23] rxgbfc[22] rxgbfc[ 21] rxgbfc[20] rxgbfc[19] rxgb fc[18] rxgbfc[ 17] rxgbfc[16] 15:8 rxgbfc[15] rxgbfc[14] rxgbfc[ 13] rxgbfc[12] rxgb fc[11] rxgbfc[10] rxgbfc[9] rxgbfc[8] 7:0 rxgbfc[7] rxgbfc[6] rxgbfc[5] rxgbfc[4] rx gbfc[3] rxgbfc[2] rxgbfc[1] rxgbfc[0] 0190h su.rxmfc 31:24 rxmfc[31] rxmfc[30] rxmfc[29] rxmfc[28] rxmfc[27] rxmfc[26] rxmfc[25] rxmfc[24] 23:16 rxmfc[23] rxmfc[22] rxmfc[21] rxmfc[20] rxmfc[19] rxmfc[18] rxmfc[17] rxmfc[16] 15:8 rxmfc[15] rxmfc[14] rxmfc[13] rxmfc[12] rx mfc[11] rxmfc[10] rxmfc[9] rxmfc[8] 7:0 rxmfc[7] rxmfc[6] rxmfc[5] rxmfc[4] rxmfc[3] rxmf c[2] rxmfc[1] rxmfc[0] 0194h su.rxcrc 31:24 rxcrc[31] rxcrc[30] rxcrc[29] rxcrc[28] rxcrc[27] rxcrc[26] rxcrc[25] rxcrc[24] 23:16 rxcrc[23] rxcrc[22] rxcrc[21] rxcrc[20] rxcrc[19] rxcrc[18] rxcrc[17] rxcrc[16] 15:8 rxcrc[15] rxcrc[14] rxcrc[13] rxcrc[12] rx crc[11] rxcrc[10] rxcrc[9] rxcrc[8] 7:0 rxcrc[7] rxcrc[6] rxcrc[5] rxcrc[4] rxcrc[3] rxcrc[ 2] rxcrc[1] rxcrc[0] 0198h su.rxalgn 31:24 rxalgn[31] rxalgn[30] rxalgn[29] rxalgn[28] rxalgn[27] rxalgn[26] rxalgn[25] rxalgn[24]
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 139 of 375 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 23:16 rxalgn[23] rxalgn[22] rxalgn[21] rxalgn[20] rxalgn[19] rxalgn[18] rxalgn[17] rxalgn[16] 15:8 rxalgn[15] rxalgn[14] rxalgn[13] rxalgn[12] rxalgn[11] rxalgn[10] rxalgn[9] rxalgn[8] 7:0 rxalgn[7] rxalgn[6] rxalgn[5] rxalgn[4] r xalgn[3] rxalgn[2] rxalgn[1] rxalgn[0] 019ch su.rxrunt 31:24 rxrunt[31 ] rxrunt[30 ] rxrunt[29 ] rxrunt[28 ] rxrunt[27 ] rxrunt[26 ] rxrunt[25 ] rxrunt[24 ] 23:16 rxrunt[23 ] rxrunt[22 ] rxrunt[21 ] rxrunt[20 ] rxrunt[19 ] rxrunt[18 ] rxrunt[17 ] rxrunt[16 ] 15:8 rxrunt[15 ] rxrunt[14 ] rxrunt[13 ] rxrunt[12 ] rxrunt[11 ] rxrunt[10 ] rxrunt[9] rxrunt[8] 7:0 rxrunt[7] rxrunt[6] rxrun t[5] rxrunt[4] rxrunt[3] rxrun t[2] rxrunt[1] rxrunt[0] 01a0h su.rxjbbr 31:24 rxjbbr[31] rxjbbr[30] rxjbbr[ 29] rxjbbr[28] rxjbbr[27] rxjbbr [26] rxjbbr[25] rxjbbr[24] 23:16 rxjbbr[23] rxjbbr[22] rxjbbr[ 21] rxjbbr[20] rxjbbr[19] rxjbbr [18] rxjbbr[17] rxjbbr[16] 15:8 rxjbbr[15] rxjbbr[14] rxjbbr [13] rxjbbr[12] rxjbbr[11] rxj bbr[10] rxjbbr[9] rxjbbr[8] 7:0 rxjbbr[7] rxjbbr[6] rxjbbr[5] rxjbbr[4] rxjbbr[3] rxjbbr[2] rxjbbr[1] rxjbbr[0] 01a4h su.rxundrsz 31:24 rxundrsz[31] rxundrsz[30] rxundrsz[29] rxundrsz[28] rxundrsz[27] rxundrsz[26] rx undrsz[25] rxundrsz[24] 23:16 rxundrsz[23] rxundrsz[22] rxundrsz[21] rxundrsz[20] rxundrsz[19] rxundrsz[18] rx undrsz[17] rxundrsz[16] 15:8 rxundrsz[15] rxundrsz[14] rxundrsz[13] rxundrsz[12] rxundrsz[11] rxundrsz[10] rx undrsz[9] rxundrsz[8] 7:0 rxundrsz[7] rxundrsz[6] rxundrsz[5] rxundrsz[4] rxundrsz[3] rxundrsz[2] rxundrsz[1] rxundrsz[0] 01a8h su.rxovrsz 31:24 rxovrsz[31] rxovrsz[30] rxovrsz[29] rxovrsz[28] rx ovrsz[27] rxovrsz[26] rxovrsz[25] rxovrsz[24] 23:16 rxovrsz[23] rxovrsz[22] rxovrsz[21] rxovrsz[20] rx ovrsz[19] rxovrsz[18] rxovrsz[17] rxovrsz[16] 15:8 rxovrsz[15] rxovrsz[14] rxovrsz[13] rxovrsz[12] rx ovrsz[11] rxovrsz[10] rxovrsz[9] rxovrsz[8] 7:0 rxovrsz[7] rxovrsz[6] rxovrsz[5] rxovrsz[4] rxovrsz[3] rxovrsz[2] rxovrsz[1] rxovrsz[0] 01ach su.rx0_64 31:24 rx0_64[31] rx0_64[30] rx0_64[29] rx0_64[28] rx0_64[27] rx0_64[26] rx0_64[25] rx0_64[24] 23:16 rx0_64[23] rx0_64[22] rx0_64[21] rx0_64[20] rx0_64[19] rx0_64[18] rx0_64[17] rx0_64[16] 15:8 rx0_64[15] rx0_64[14] rx0_64[13] rx0_64[12] rx0_64[11] rx0_64[10] rx0_64[9] rx0_64[8] 7:0 rx0_64[7] rx0_64[6] rx0_64[5] rx0_64[4] rx0_64[3] rx0_64[2] rx0_64[1] rx0_64[0] 01b0h su.rx65_127 31:24 rx65_127[31] rx65_127[30] rx65_127[29] rx65_127[28] r x65_127[27] rx65_127[26] rx65_127[25] rx65_127[24] 23:16 rx65_127[23] rx65_127[22] rx65_127[21] rx65_127[20] r x65_127[19] rx65_127[18] rx65_127[17] rx65_127[16] 15:8 rx65_127[15] rx65_127[14] rx65_127[13] rx65_127[12] r x65_127[11] rx65_127[10] rx65_127[9] rx65_127[8] 7:0 rx65_127[7] rx65_127[6] rx65_127[5] rx65_127[4] rx65_127[3] rx65_1 27[2] rx65_127[1] rx65_127[0] 01b4h su.rx128_255 31:24 rx128_255[31] rx128_255[30] rx128_255[29] rx128_255[28] rx128_255[27] rx128_255[26] rx128_255[25] rx128_255[24] 23:16 rx128_255[23] rx128_255[22] rx128_255[21] rx128_255[20] rx128_255[19] rx128_255[18] rx128_255[17] rx128_255[16] 15:8 rx128_255[15] rx128_255[14] rx128_255[13] rx128_255[12] rx128_255[11] rx128_255[10] rx128_255[9] rx128_255[8] 7:0 rx128_255[7] rx128_255[6] rx128_255[5] rx128_255[4] rx128_255[3] rx128_255[2] rx128_255[1] rx128_255[0] 01b8h su.rx256_511 31:24 rx256_511[31] rx256_511[30] rx256_511[29] rx256_511[28] rx256_511[27] rx256_511[26] rx256_511[25] rx256_511[24] 23:16 rx256_511[23] rx256_511[22] rx256_511[21] rx256_511[20] rx256_511[19] rx256_511[18] rx256_511[17] rx256_511[16] 15:8 rx256_511[15] rx256_511[14] rx256_511[13] rx256_511[12] rx256_511[11] rx256_511[10] rx256_511[9] rx256_511[8] 7:0 rx256_511[7] rx256_511[6] rx256_511[5] rx256_511[4] rx256_511[3] rx256_511[2] rx256_511[1] rx256_511[0] 01bch su.rx512_1k 31:24 rx512_1k[31] rx512_1k[30] rx512_1k[29] rx512_1k[28] rx512_1k[27] rx512_1k[26] rx512_1k[25] rx512_1k[24] 23:16 rx512_1k[23] rx512_1k[22] rx512_1k[21] rx512_1k[20] rx512_1k[19] rx512_1k[18] rx512_1k[17] rx512_1k[16] 15:8 rx512_1k[15] rx512_1k[14] rx512_1k[13] rx512_1k[12] rx512_1k[11] rx512_1k[10] rx512_1k[9] rx512_1k[8] 7:0 rx512_1k[7] rx512_1k[6] rx512_1k[5] rx512_1k[4] rx512_1k[3] rx512_1k[2] rx512_1k[1] rx512_1k[0] 01c0h su.rx1k_max 31:24 rx1k_max[31] rx1k_max[30] rx1k_max[29] rx1k_max[28] rx1k_max[27] rx1k_max[26] rx1k_max[25] rx1k_max[24]
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 140 of 375 a ddr n ame b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 23:16 rx1k_max[23] rx1k_max[22] rx1k_max[21] rx1k_max[20] rx1k_max[19] rx1k_max[18] rx1k_max[17] rx1k_max[16] 15:8 rx1k_max[15] rx1k_max[14] rx1k_max[13] rx1k_max[12] rx1k_max[11] rx1k_max[10] rx1k_max[9] rx1k_max[8] 7:0 rx1k_max[7] rx1k_max[6] rx1k_max[5] rx1k_max[4] rx1k_max[3] rx1k_max[2] rx1k_max[1] rx1k_max[0] 01c4h su.rxufc 31:24 rxufc[31] rxufc[30] rxufc[29] rxufc[28] rxufc[27] rxufc[26] rxufc[25] rxufc[24] 23:16 rxufc[23] rxufc[22] rxufc[21] rxufc[20] rxufc[19] rxufc[18] rxufc[17] rxufc[16] 15:8 rxufc[15] rxufc[14] rxufc[13] rxufc[12] rxufc[11] rxufc[10] rxufc[9] rxufc[8] 7:0 rxufc[7] rxufc[6] rxufc[5] rxufc[4] rxufc[3] rxufc[2] rxufc[1] rxufc[0] 01c8h su.rxlnerr 31:24 rxlnerr[31] rxlnerr[30] rxlnerr[ 29] rxlnerr[28] rxlnerr[27] rxlnerr[ 26] rxlnerr[25] rxlnerr[24] 23:16 rxlnerr[23] rxlnerr[22] rxlnerr[ 21] rxlnerr[20] rxlnerr[19] rxlnerr[ 18] rxlnerr[17] rxlnerr[16] 15:8 rxlnerr[15] rxlnerr[14] rxlnerr[ 13] rxlnerr[12] rxlnerr[11] rxlnerr[10] rxlnerr[9] rxlnerr[8] 7:0 rxlnerr[7] rxlnerr[6] rxlnerr[5] rxlnerr[4] rxlnerr[3] rxlnerr[2] rxlnerr[1] rxlnerr[0] 01cch su.rxrange 31:24 rxrange[31] rxrange[30] rxrang e[29] rxrange[28] rxrange[27] rxrang e[26] rxrange[25] rxrange[24] 23:16 rxrange[23] rxrange[22] rxrang e[21] rxrange[20] rxrange[19] rxrang e[18] rxrange[17] rxrange[16] 15:8 rxrange[15] rxrange[14] rxrang e[13] rxrange[12] rxrange[11] rxrang e[10] rxrange[9] rxrange[8] 7:0 rxrange[7] rxrange[6] rxrang e[5] rxrange[4] rxrange[3] rxrang e[2] rxrange[1] rxrange[0] 01d0h su.rxpause 31:24 rxpause[31] rxpause[30] rxpause[29] rxpause[28] rx pause[27] rxpause[26] rxpause[25] rxpause[24] 23:16 rxpause[23] rxpause[22] rxpause[21] rxpause[20] rx pause[19] rxpause[18] rxpause[17] rxpause[16] 15:8 rxpause[15] rxpause[14] rxpause[13] rxpause[12] rxpause[11] rxpause[10] rxpause[9] rxpause[8] 7:0 rxpause[7] rxpause[6] rxpause[5] rxpause[4] rxpause[3] rxpause[2] rxpause[1] rxpause[0] 01d4h su.rxovfl 31:24 rxovfl[31] rxovfl[30] rxovfl[29] rxovfl[28] rxovfl[27] rxovfl[26] rxovfl[25] rxovfl[24] 23:16 rxovfl[23] rxovfl[22] rxovfl[21] rxovfl[20] rxovfl[19] rxovfl[18] rxovfl[17] rxovfl[16] 15:8 rxovfl[15] rxovfl[14] rxovfl[13] rxovfl[12] rxovfl[11] rxovfl[10] rxovfl[9] rxovfl[8] 7:0 rxovfl[7] rxovfl[6] rxovfl[5] rxovfl[4] rxovfl[3] rxovfl[2] rxovfl[1] rxovfl[0] 01d8h su.rxvlan 31:24 rxvlan[31] rxvlan[30] rxvlan[29] rxvlan[28] rxvlan[27] rxvlan[26] rxvlan[25] rxvlan[24] 23:16 rxvlan[23] rxvlan[22] rxvlan[21] rxvlan[20] rxvlan[19] rxvlan[18] rxvlan[17] rxvlan[16] 15:8 rxvlan[15] rxvlan[14] rxvlan[13] rxvlan[12] rxvlan[11] rxvlan[10] rxvlan[9] rxvlan[8] 7:0 rxvlan[7] rxvlan[6] rxvlan[5] rxvlan[4] rxvlan[3] rxvlan[2] rxvlan[1] rxvlan[0] 01dch su.rxwdog 31:24 rxwdog[31] rxwdog[30] rxwdog[29] rxwdog[28] rx wdog[27] rxwdog[26] rxwdog[25] rxwdog[24] 23:16 rxwdog[23] rxwdog[22] rxwdog[21] rxwdog[20] rx wdog[19] rxwdog[18] rxwdog[17] rxwdog[16] 15:8 rxwdog[15] rxwdog[14] rxwdog[13] rxwdog[12] rxwdog[11] rxwdog[10] rxwdog[9] rxwdog[8] 7:0 rxwdog[7] rxwdog[6] rxwdog[5] rxwdog[4] rxwdog[3] rxwdog[2] rxwdog[1] rxwdog[0] 1018h su.macmcr 31:24 - - - - - - - - 23:16 - - - ftf - - - - 15:8 - - - - - - - - 7:0 - - - - - - - - note that the addresses in the table above are t he indirect addresses that must be provided to the su.mac1awh and su.mac1awl. all unused and reserved locations must be initialized to zero for proper operation unless specifically noted otherwise.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 141 of 375 10.2 global register definitions note that although most registers are defined as 16- bit registers, the constituent bytes are accessed through the parallel or spi interfaces one byte at a time. individual address locations are defined for each byte. register name: gl.idr register description: global id register register address: 000h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 001h: rev2 rev1 rev0 spis vc2 vc1 vc0 vcat default 0 - - - - - 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000h: wp4 wp3 wp2 wp1 wp0 gbe mp1 mp0 default - - - - - 0 - - bits 13-15: revision number (rev[2:0]) contains a sequential number that is related to, but not equal to, the device revision on the top brand. silic on revision numbering begins at 000. bit 12: spi slave (spis) if this bit is set to 1, the device only supports a spi slave microprocessor port. bits 9-11: voice channels (vc[2:0]) this contains the number of voice channels supported. bit 8: vcat (vcat) if this bit is set to 1, the device has vcat functionality. bits 3-7: serial wan ports (wp[4:0]) these bits contain the number of wan ports in the device. bit 3: gigabit ethernet support (gbe) if this bit is set, the device support gbe. bits 0-1: ethernet lan ports (mp[1:0]) these bits contain the number of mac ports in the device. table 10-4. default gl.idr values device spis vc[2:0] vcat wp[4:0] gbe mp[1:0] DS33X162 0 000 1 10000 1 10 ds33x161 0 000 1 10000 1 01 ds33x82 0 000 1 01000 1 10 ds33x81 0 000 1 01000 1 01 ds33x42 0 000 1 00100 1 10 ds33x41 0 000 1 00100 1 01 ds33w41 0 001 1 00100 1 01 ds33x11 1 000 1* 00001 1 01 ds33w11 0 001 1* 00001 1 01 *note, the single-port ds33x11 and ds 33w11 devices support reservation of the vcat overhead byte position as required by itu-t g.8040, not the ac tual concatenation of wan links.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 142 of 375 register name: gl.cr1 register description: global control register 1 register address: 002h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 003h: - - p2spd - p1spd - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 002h: - - - - - fmc-2 fmc-1 fmc-0 default 0 0 0 0 0 0 0 0 bit 13: lan port 2 speed selection (p2spd) 0 = 10mbps operation 1 = 100mbps bit 11: lan port 1 speed selection (p1spd) 0 = 10mbps operation 1 = 100mbps operation this bit setting is only applicable to mii and rmii modes. bits 0-2: forwarding mode control (fmc[2:0]) 000 = reserved 001 = forwarding mode 1. single ethernet port with priority forwarding . in this mode, ethernet frames are segregated into up to four priority levels and forwarded to separate wan data streams. 010 = forwarding mode 2. per-ethernet-port forwarding with priority scheduling . in this mode, frames from each ethernet port are forwarded to their own group of four priori ty queues, generating two separate wan data streams with priority scheduled traffic. 011 = forwarding mode 3. single ethernet port with vlan forwarding and priority scheduling . in this mode, ethernet frames are forwarded by vlan tag (v id) into up to four groups of four priority queues (wan groups) each. each wan group forms a separate wan data stream with priority scheduled traffic. 100 = forwarding mode 4. per-ethernet-port forwarding, with vlan forwarding and priority scheduling within each vlan group . in this mode, ethernet frames from each ethernet port are forwarded separately, by vlan tag, into two sets of four priority queues (wan groups) each. the two wan groups form separate wan data st reams with priority scheduled traffic. 101 = forwarding mode 5. full vlan forwarding in both the lan-to-wan and wan-to-lan directions . in this mode, ethernet frames from both ports can be forwarded by vlan tag to two shared wan groups. within each wan group, there are two sets of four priority queues. the two sets of priority queues are serviced with a round- robin algorithm. frames received from the wan side can be forwarded by vlan tag to either ethernet port. the lan-to-wan and wan-to-lan mappings are independent and can be configured separately. 110 = reserved. 111 = reserved. in all forwarding modes, vcat/lcas can be used to aggr egate multiple physical serial ports for each wan group?s data stream, except on devices that do not support vcat/lcas.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 143 of 375 register name: gl.cr2 register description: global control register 2 register address: 004h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 005h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 004h: - - - - intm endel - rst default 0 0 0 0 0 0 0 0 bit 3: interrupt mode (intm) when this bit is set to 1, the inactive state of the int pin will be high-impedance. when this bit is equal to 0, the inactive state of the int pin will be a driven logic high. bit 2: encap/decap loopback (endel) when this bit is set to 1, the wan-side output data from encapsulator #1 is looped back to the wan input of decapsulator #1. bit 0: global reset (rst) when this bit is set, all of the internal dat a path, status, and contro l registers (except the rst bit), on all ports, will be reset to the default state. th is bit must remain set to 1 for a minimum of 100ns to initiate the reset operation. the bit should be cleared to 0 for normal operation to resume. note that setting this bit does not tri-state output pins. when using a revision a1 ( gl.idr.revn=000) device in spi mode, the individual block reset bits or the hardware reset pin should be used instead of this bit.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 144 of 375 register name: gl.isr register description: global interrupt status register register address: 008h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 009h: micis decis4 decis3 decis2 ecis4 ecis3 ecis2 rvcatis default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 008h: - bufis - tspis decis1 ecis1 txlanis rxlanis default 0 0 0 0 0 0 0 0 bit 15: microprocessor interrupt status (micis) this bit is set if the microport has an active, enabled interrupt condition. normally, this condition is caused by the pr esence of a trapped frame for extraction and processing. bit 14: decapsulation interrupt status 4 (decis4) this bit is set if decapsulator 4 has an active, enabled interrupt condition. bit 13: decapsulation interrupt status 3 (decis3) this bit is set if decapsulator 3 has an active, enabled interrupt condition. bit 12: decapsulation interrupt status 2 (decis2) this bit is set if decapsulator 2 has an active, enabled interrupt condition. bit 11: encapsulation interrupt status 4 (ecis4) this bit is set if encapsulator 4 has an active, enabled interrupt condition. bit 10: encapsulation interrupt status 3 (ecis3) this bit is set if encapsulator 3 has an active, enabled interrupt condition. bit 9: encapsulation interrupt status 2 (ecis2) this bit is set if encapsulator 2 has an active, enabled interrupt condition. bit 8: receive vcat interrupt status (rvcatis) this bit is set if the receive vcat has an active, enabled interrupt condition. bit 6: buffer manager (arbiter) interrupt status (bufis) this bit is set if the buffer manager has an active, enabled interrupt condition. bit 4: transmit wan serial port interrupt status (tspis) this bit is set if the transmit serial wan port has an active, enabled interrupt condition. bit 3: decapsulation interrupt status 1 (decis1) this bit is set if decapsulator 1 has an active, enabled interrupt condition. bit 2: encapsulation interrupt status 1 (ecis1) this bit is set if encapsulator 1 has an active, enabled interrupt condition. bit 1: transmit lan interrupt status (txlanis) this bit is set if a transmit ethernet lan port has an active, enabled interrupt condition. bit 0: receive lan and bridge filter interrupt status (rxlanis) this bit is set if either of the receive ethernet lan mac(s) or the lan queue overflows ha ve an active, enabled interrupt condition.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 145 of 375 register name: gl.ier register description: global interrupt enable register register address: 00ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00bh: micie decie4 decie3 decie2 ecie4 ecie3 ecie2 rvcatie default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00ah: - bufie - tspie decie1 ecie1 txlanie rxlanie default 0 0 0 0 0 0 0 0 bit 15: microport interrupt enable (micie) when this bit is set to 1, micis will generate an interrupt. bit 14: decapsulation interrupt enable 4 (decie4) when this bit is set to 1, decis4 will generate an interrupt. bit 13: decapsulation interrupt enable 3 (decie3) when this bit is set to 1, decis3 will generate an interrupt. bit 12: decapsulation interrupt enable 2 (decie2) when this bit is set to 1, decis2 will generate an interrupt. bit 11: encapsulation interrupt enable 4 (ecie4) when this bit is set to 1, ecis4 will generate an interrupt. bit 10: encapsulation interrupt enable 3 (ecie3) when this bit is set to 1, ecis3 will generate an interrupt. bit 9: encapsulation interrupt enable 2 (ecie2) when this bit is set to 1, ecis2 will generate an interrupt. bit 8: receive vcat interrupt enable (rvcatie) when this bit is set to 1, rvcatis will generate an interrupt. bit 6: buffer manager (arbiter) interrupt enable (bufie) when this bit is set to 1, bufis will generate an interrupt. bit 4: transmit wan serial port interrupt enable (tspie) when this bit is set to 1, tspis will generate an interrupt. bit 3: decapsulation inte rrupt enable 1 (decie1) when this bit is set to 1, decis1 will generate an interrupt. bit 2: encapsulation interrupt enable 1 (ecie1) when this bit is set to 1, ecis1 will generate an interrupt. bit 1: transmit lan interrupt enable (txlanie) when this bit is set to 1, txlanis will generate an interrupt. bit 0: receive lan and bridge filter interrupt enable (rxlanie) when this bit is set to 1, rxlanis will generate an interrupt.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 146 of 375 register name: gl.mbsr register description: global pll status register register address: 00ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00dh: - - - - dlock plock - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00ch: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 11: dpll lock (dlock) this bit is set to 1 if the dpll has achieved lock. bit 10: pll lock (plock) this bit is set to 1 if pll has achieved lock.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 147 of 375 10.2.1 microport registers register name: gl.mcr1 register description: microport control register 1 register address: 020h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 021h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 020h: - - - - - - fifo1 fifo0 default 0 0 0 0 0 0 0 0 bits 0-1: fifo[1:0] fifo selection these bits select which fifo will be accessed for reading or writing. 00 = wan insertion fifo 01 = wan extraction fifo 10 = lan insertion fifo 11 = lan extraction fifo register name: gl.mcr2 register description: microport control register 2 register address: 022h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 023h: - - - - wilen11 wilen10 wilen9 wilen8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 022h: wilen7 wilen6 wilen5 wilen4 wilen3 wilen2 wilen1 wilen0 default 0 0 0 0 0 0 0 0 bits 0-11: wan insertion frame length (wilen[11:0]) these bits determine the number of bytes of the frame to be written to fifo selected (insertion fifos only). maximum size frame is 2048 bytes.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 148 of 375 register name: gl.mcr3 register description: microport control register 3 register address: 024h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 025h: - - - - lilen11 lilen10 lilen9 lilen8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 024h: lilen7 lilen6 lilen5 lilen4 lilen3 lilen2 lilen1 lilen0 default 0 0 0 0 0 0 0 0 bits 0-11: lan insertion frame length (lilen[11:0]) these bits determine the number of bytes of the frame to be written to fifo selected (insertion fifos only). maximum size frame is 2048 bytes. register name: gl.msr1 register description: microport status register 1 register address: 026h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 027h: - - - - welen11 welen10 welen9 welen8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 026h: welen7 welen6 welen5 welen4 welen3 welen2 welen1 welen0 default 0 0 0 0 0 0 0 0 bits 0-11: wan extraction frame length (welen[11:0]) these bits report the size of the frame in bytes available in the wan extraction fifo. maximum size frame is 2048 bytes. this value is updated when a complete frame is received in the wan extraction fifo. register name: gl.msr2 register description: microport status register 2 register address: 028h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 029h: - - - - lilen11 lelen10 lelen9 lelen8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 028h: lelen7 lelen6 lelen5 lelen4 lelen3 lelen2 lelen1 lelen0 default 0 0 0 0 0 0 0 0 bits 0-11: lan extraction frame length (lelen[11:0]) these bits report the size of the frame in bytes available in the lan extraction fifo. maximum size frame is 2048 by tes. this value is updated when a complete frame is received in the lan extraction fifo.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 149 of 375 register name: gl.msr3 register description: microport status register 3 register address: 02ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 02bh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02ah: - - - - lanea lanie wanea wanie default 0 0 0 0 0 0 0 0 bit 3: lan extraction available (lanea) set when the lan extraction fifo has a frame available to read. clears when the first byte is read from the fifo. bit 2: lan insertion queue empty (lanie) set when the lan insertion fifo is empty. bit 1: wan extraction available (wanea) set when the wan extraction fifo has a frame available to read. clears when the first byte is read from the fifo bit 0: wan insertion queue empty (wanie) set when the wan insertion fifo is empty. register name: gl.mlsr3 register description: microport latched status register 3 register address: 02ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 02dh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02ch: - - - - laneal laniel waneal waniel default 0 0 0 0 0 0 0 0 bit 3: lan extraction available - latched (laneal) set when the lan extraction fifo has a frame available to read. clears when the first byte is read from the fifo. bit 2: lan insertion empty - latched (laniel) set when the lan insertion fifo is empty. bit 1: wan extraction available - latched (waneal) set when the wan extraction fifo has a frame available to read. clears when the first byte is read from the fifo. bit 0: wan insertion empty - latched (waniel) set when the wan insertion fifo is empty.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 150 of 375 register name: gl.msier3 register description: microport status interrupt enable register 3 register address: 02eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 02fh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02eh: - - - - laneaie lanieie waneaie wanieie default 0 0 0 0 0 0 0 0 bit 3: lan extraction available interrupt enable (laneaie) this bit enables laneal to cause an interrupt. 0 = interrupt disabled 1 = interrupt enabled bit 2: lan insertion empty in terrupt enable (lanieie) this bit enables an interrupt if the laniel bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: wan extraction available interrupt enable (waneaie) this bit enables waneal to cause an interrupt. 0 = interrupt disabled 1 = interrupt enabled bit 0: wan insertion empty interrupt enable (wanieie) this bit enables an interrupt if the waniel bit is set. 0 = interrupt disabled 1 = interrupt enabled register name: gl.mfawr register description: microport fifo access write register register address: 030h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 031h: - - - - - - rd_dn wr_dn default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 030h: wpkt7 wpkt6 wpkt5 wpkt4 wpkt3 wpkt2 wpkt1 wpkt0 default 0 0 0 0 0 0 0 0 bit 9: read byte (rd_dn) a zero-to-one transition is required after the last byte of the frame has been read from the mfawr register. this signals the associated fifo (wan extract or lan extract) to reset its pointers. bit 8: write byte (wr_dn) a zero-to-one transition is required after the last byte of the frame has been written to mfawr register. this transition signals that the frame is ready to be transferred. bits 0-7: packet write byte (wpkt[7:0]) if an insertion fifo is selected, this register inserts a byte of frame data into the fifo selected by mcr2. the beginning of the frame to be transmitted is written first. each write automatically increments the fifo pointer. if an extraction fi fo is selected, this register reports a byte of frame data from the fifo selected by mcr2. the beginning of the frame to be transmitted is read first. each read automatically increments the fifo pointer.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 151 of 375 register name: gl.mfarr register description: microport fifo access read register register address: 032h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 033h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 032h: rpkt7 rpkt6 rpkt5 rpkt4 rpkt3 rpkt2 rpkt1 rpkt0 default 0 0 0 0 0 0 0 0 bits 0-7: packet read byte (rpkt[7:0]) if an extraction fifo is selected, this register reports a byte of frame data from the fifo selected by mcr1. the beginning of the frame to be transmitted is read first. each read automatically increments the fifo pointer.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 152 of 375 10.2.2 mac 1 interface access registers register name: su.mac1radl register description: mac 1 read address low register register address: 040h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 040h: macra7 macra6 macra5 macra4 macra3 macra2 macra1 macra0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read address (macra0-7) - low byte of the mac address. used only for read operations. register name: su.mac1radh register description: mac 1 read address high register register address: 041h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 041h: macra15 macra14 macra13 macra12 macra11 macra10 macra9 macra8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read address (macra8-15) - high byte of the mac address. used only for read operations. register name: su.mac1rd0 register description: mac 1 read data byte 0 register address: 042h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 042h: macrd7 macrd6 macrd5 macrd4 macrd3 macrd2 macrd1 macrd0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 0 (macrd0-7): one of four bytes of data read from the mac. valid after a read command has been issued and the su.mac1rwc.mcs bit is zero.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 153 of 375 register name: su.mac1rd1 register description: mac 1 read data byte 1 register address: 043h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 043h: macrd15 macrd14 macrd13 macrd12 macrd11 macrd10 macrd9 macrd8 default 0 0 0 0 0 0 0 0 bits 0 - 7: mac read data 1 (macrd8-15) - one of four bytes of data read from the mac. valid after a read command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac1rd2 register description: mac 1 read data byte 2 register address: 044h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 044h: macrd23 macrd22 macrd21 macrd20 macrd19 macrd18 macrd17 macrd16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 2 (macrd16-23) - one of four bytes of data read from the mac. valid after a read command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac1rd3 register description: mac 1 read data byte 3 register address: 045h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 045h: macrd31 macrd30 macrd29 macrd28 macrd27 macrd26 macrd25 macrd24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 3 (macrd24-31) - one of four bytes of data read from the mac. valid after a read command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac1wd0 register description: mac 1 write data byte 0 register address: 046h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 046h: macwd7 macwd6 macwd5 macwd4 macwd3 macwd2 macwd1 macwd0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 0 (macwd0-7) - one of four bytes of data to be wr itten to the mac. data has been written after a write command has been issued and the su.mac1rwc.mcs bit is zero.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 154 of 375 register name: su.mac1wd1 register description: mac 1 write data byte 1 register address: 047h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 047h: macwd15 macwd14 macwd13 macwd12 macwd11 macwd10 macwd09 macwd08 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 1 (macwd8-15) - one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac1wd2 register description: mac 1 write data byte 2 register address: 048h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 048h: macwd23 macwd22 macwd21 macwd20 macwd19 macwd18 macwd17 macwd16 default 0 0 0 0 0 0 0 0 bits 0 - 7: mac write data 2 (macwd16-23) - one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac1wd3 register description: mac 1 write data byte 3 register address: 049h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 049h: macd31 macd30 macd 29 macd28 macd27 ma cd26 macd25 macd24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 3 (macd24-31) - one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac1awl register description: mac 1 address write low register address: 04ah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04ah: macaw7 macaw6 macaw5 macaw4 macaw3 macaw2 macaw1 macaw0 default 0 0 0 0 0 0 0 0 bits 0 -7: mac write address (macaw0-7) - low byte of the mac address. used only for write operations.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 155 of 375 register name: su.mac1awh register description: mac 1 address write high register address: 04bh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04bh: macaw15 macaw14 macaw13 macaw12 macaw11 macaw10 macaw9 macaw8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write address (macaw8-15) - high byte of the mac address. used only for write operations. register name: su.mac1rwc register description: mac 1 read write command status register address: 04ch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04ch: - - - - - - mcrw mcs default 0 0 0 0 0 0 0 0 bit 1: mac command rw ? if this bit is written to 1, a read is performed from the mac. if this bit is written to 0, a write operation is performed. address information for write operations must be located in su.mac1awh and su.mac1awl . address information for read operations must be located in su.mac1radh and su.mac1radl . the user must also write a 1 to the mcs bit, and the device will clear mcs when the operation is complete. bit 0: mac command status ? setting mcs in conjunction with mcrw wi ll initiate a read or write to the mac registers. upon completion of the read or write this bit is cleared. once a read or write command has been initiated the host must poll this bit to see when the operation is complete.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 156 of 375 10.2.3 mac 2 interface access registers register name: su.mac2radl register description: mac 2 read address low register register address: 060h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 060h: macra7 macra6 macra5 macra4 macra3 macra2 macra1 macra0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read address (macra0-7) - low byte of the mac address. used only for read operations. register name: su.mac2radh register description: mac 2 read address high register register address: 061h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 061h: macra15 macra14 macra13 macra12 macra11 macra10 macra9 macra8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read address (macra8-15) - high byte of the mac address. used only for read operations. register name: su.mac2rd0 register description: mac 2 read data byte 0 register address: 062h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 062h: macrd7 macrd6 macrd5 macrd4 macrd3 macrd2 macrd1 macrd0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 0 (macrd0-7): one of four bytes of data read from the mac. valid after a read command has been issued and the su.mac1rwc.mcs bit is zero.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 157 of 375 register name: su.mac2rd1 register description: mac 2 read data byte 1 register address: 063h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 063h: macrd15 macrd14 macrd13 macrd12 macrd11 macrd10 macrd9 macrd8 default 0 0 0 0 0 0 0 0 bits 0 - 7: mac read data 1 (macrd8-15) - one of four bytes of data read from the mac. valid after a read command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac2rd2 register description: mac 2 read data byte 2 register address: 064h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 064h: macrd23 macrd22 macrd21 macrd20 macrd19 macrd18 macrd17 macrd16 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 2 (macrd16-23) - one of four bytes of data read from the mac. valid after a read command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac2rd3 register description: mac 2 read data byte 3 register address: 065h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 065h: macrd31 macrd30 macrd29 macrd28 macrd27 macrd26 macrd25 macrd24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac read data 3 (macrd24-31) - one of four bytes of data read from the mac. valid after a read command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac2wd0 register description: mac 2 write data byte 0 register address: 066h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 066h: macwd7 macwd6 macwd5 macwd4 macwd3 macwd2 macwd1 macwd0 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 0 (macwd0-7) - one of four bytes of data to be wr itten to the mac. data has been written after a write command has been issued and the su.mac1rwc.mcs bit is zero.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 158 of 375 register name: su.mac2wd1 register description: mac 2 write data byte 1 register address: 067h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 067h: macwd15 macwd14 macwd13 macwd12 macwd11 macwd10 macwd09 macwd08 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 1 (macwd8-15) - one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac2wd2 register description: mac 2 write data byte 2 register address: 068h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 068h: macwd23 macwd22 macwd21 macwd20 macwd19 macwd18 macwd17 macwd16 default 0 0 0 0 0 0 0 0 bits 0 - 7: mac write data 2 (macwd16-23) - one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac2wd3 register description: mac 2 write data byte 3 register address: 069h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 069h: macd31 macd30 macd 29 macd28 macd27 ma cd26 macd25 macd24 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write data 3 (macd24-31) - one of four bytes of data to be written to the mac. data has been written after a write command has been issued and the su.mac1rwc.mcs bit is zero. register name: su.mac2awl register description: mac 2 address write low register address: 06ah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 06ah: macaw7 macaw6 macaw5 macaw4 macaw3 macaw2 macaw1 macaw0 default 0 0 0 0 0 0 0 0 bits 0 -7: mac write address (macaw0-7) - low byte of the mac address. used only for write operations.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 159 of 375 register name: su.mac2awh register description: mac 2 address write high register address: 06bh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 06bh: macaw15 macaw14 macaw13 macaw12 macaw11 macaw10 macaw9 macaw8 default 0 0 0 0 0 0 0 0 bits 0 ? 7: mac write address (macaw8-15) - high byte of the mac address. used only for write operations. register name: su.mac2rwc register description: mac 2 read write command status register address: 06ch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 06ch: - - - - - - mcrw mcs default 0 0 0 0 0 0 0 0 bit 1: mac command rw ? if this bit is written to 1, a read is performed from the mac. if this bit is written to 0, a write operation is performed. address information for write operations must be located in su.mac1awh and su.mac1awl . address information for read operations must be located in su.mac1radh and su.mac1radl . the user must also write a 1 to the mcs bit, and the device will clear mcs when the operation is complete. bit 0: mac command status ? setting mcs in conjunction with mcrw wi ll initiate a read or write to the mac registers. upon completion of the read or write this bit is cleared. once a read or write command has been initiated the host must poll this bit to see when the operation is complete.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 160 of 375 10.2.4 vlan control registers register name: su.vtc register description: vlan table control register address: 080h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 081h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 080h: - - - - - cte ci caim default 0 0 0 0 0 0 0 0 this register is used to control the vlan table. the initia lization function resets all of the 4096 entries in the vlan table to their default value. bit 2: control table enable (cte) when equal to zero, the vlan table is fully enabled. when set to 1, the vlan table is only enabled as required by the lan extrac t (lan-vlan trap), wan extract (wan-vlan trap), or microprocessor operations. bit 1: control initialization (ci). a transition from zero to one starts the vlan table initialization by resetting all vlan table addresses to their default values. a device reset will also tr igger a vlan table initialization. bit 0: control auto increment mode (caim). when set to 1, the vlan table address in su.vtaa is automatically incremented with each read or write of the su.vtwd or su.vtrd registers. register name: su.vtaa register description: vlan table access address register address: 082h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 083h: - - - - vtaa12 vtaa11 vtaa10 vtaa9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 082h: vtaa8 vtaa7 vtaa6 vtaa5 vtaa4 vtaa3 vtaa2 vtaa1 default 0 0 0 0 0 0 0 0 the data that is stored at the specifie d vlan table address is automatically loaded into the read register for this configuration register address. this is true whether the us er is performing a read or write function. the user may choose to read the data (for the read operation) or disregard the data (for the write operation). bits 0-11: vlan table access address (vtaa [12:1]). this register provides the vlan table address for a up read or write operation.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 161 of 375 register name: su.vtwd register description: vlan table write data register address: 084h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 085h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 084h: - - wvefw wvqfw lvdw lvefw lvqfw2 lvqfw1 default 0 0 0 0 0 0 0 0 whenever a write is performed to this configuration register add ress the data is stored in the vlan table at the address specified by the su.vtaa register (i.e. the vtaa value must be provided in advance of the vtwd data). vlan forwarding, extracting (trapping), or discarding. each address ( su.vtaa ) in the vlan table corresponds to a specific vlan id (vid) value from 0 to 4095 , and the bit settings at each address relate to actions taken when a frame containing the corresponding vlan id value is detected. these values are used to translate vlan tag information from each received frame into forwarding, trappi ng (frame extraction), or discarding decisions. the user may configure any or all of the 4096 vl an ids values in the vlan table. the data written to this register is stored in the vlan tabl e at the specified vlan table address. bit 5: wan-vlan extract forwarding (wan-vlan trap) (wvefw) 0 = do nothing. 1 = trap frames received from the wan with th is vid and place them in the wan extract queue. bit 4: wan-vlan queue forwarding (wvqfw; only valid in forwarding mode 5) 0 = forward frames received from the wan with this vid value to ethernet port 1 1 = forward frames received from the wan with this vid value to ethernet port 2 bit 3: lan-vlan discard (lvdw) 0 = do nothing. 1 = discard frames received from the lan with this vid bit 2: lan-vlan extract forwarding (lan-vlan trap) (lvefw) 0 = do not forward this frame to the lan extract queue 1 = forward this frame to the lan extract queue bits 0-1: lan-vlan queue forwarding (lvqfw [2:1]) 00 = forward frames with a vid value equal to this table address to lan queue group 1 01 = forward frames with a vid value equal to this table address to lan queue group 2 10 = forward frames with a vid value equal to this table address to lan queue group 3 11 = forward frames with a vid value equal to this table address to lan queue group 4 note: lan extract forwarding takes prec edence over lan queue forwarding. lan discard takes precedence over lan extract forwarding (trapping). wan extract forwarding (trapping) take s precedence over wan queue forwarding.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 162 of 375 register name: su.vtrd register description: vlan table read data register address: 086h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 087h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 086h: - - wvefr wvqfr lvdr lvefr lvqfr2 lvqfr1 default 0 0 0 0 0 0 0 0 whenever a read operation is performed on this configurat ion register, the data stored in the vlan table at the address specified by the su.vtaa register is read. the vtaa value must be initialized prior to the read operation. vlan forwarding. these values determine whether to forward a frame to an extract or forwarding queue or (in the lan to wan direction) whether to discard the frame, there are 4096 vlan ids. the user may configure any number of these 4096 vlan ids. the data in this register provides the read data that was retrieved from a vlan table read operation. bit 5: wan-vlan extract forwarding (wan-vlan trap) (wvefr) 0 = do nothing. 1 = trap frames received from the wan with th is vid and place them in the wan extract queue. bit 4: wan-vlan queue forwarding (wvqfr; only valid in forwarding mode 5) 0 = forward frames received from the wan with this vid value to ethernet port 1 1 = forward frames received from the wan with this vid value to ethernet port 2 bit 3: lan-vlan discard (lvdr) 0 = do nothing. 1 = discard frames received from the lan with this vid bit 2: lan-vlan extract forwarding (lan-vlan trap) (lvefr) 0 = do not forward this frame to the lan extract queue 1 = forward this frame to the lan extract queue bits 0-1: lan-vlan queue forwarding (lvqfr[2:1]) 00 = forward frames with a vid value equal to this table address to lan queue group 1 01 = forward frames with a vid value equal to this table address to lan queue group 2 10 = forward frames with a vid value equal to this table address to lan queue group 3 11 = forward frames with a vid value equal to this table address to lan queue group 4 note: lan extract forwarding takes prec edence over lan queue forwarding. lan discard takes precedence over lan extract forwarding (trapping). wan extract forwarding (trapping) take s precedence over wan queue forwarding.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 163 of 375 register name: su.vtsa register description: vlan table shadow address register address: 088h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 089h: - - - vtis vtsa12 vtsa11 vtsa10 vtsa9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 088h: vtsa8 vtsa7 vtsa6 vtsa5 vtsa4 vtsa3 vtsa2 vtsa1 default 0 0 0 0 0 0 0 0 bit 12: vlan table initia lization status (vtis): this bit is set to 1 when the vlan table initialization has been completed. occurs upon reset. bits 0-11: vlan table shadow address (vtsa [12:1]) this register interfaces directly to the vlan table memory block to provide the selected vlan table addres s that is to be used for each vlan table operation (lan trap, wan trap or up read/write). when su.vtc.caim = 1, the shadow address aut omatically increments for each read and/or write vlan table access.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 164 of 375 10.3 ethernet interface registers the ethernet interface registers are used to configure gmii/mii/rmii bus operation and establish the mac parameters as required by the user. the mac registers cannot be addressed di rectly from the processor port. the registers below are used to perform indirect read or write operations to the mac registers. the mac status registers are shown in table 10-3. accessing the mac registers is described in section 8.19. 10.3.1 wan extraction and transmit lan registers register name: su.wem register description: wan extract modes and ethernet tag settings register address: 0a0h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0a1h: - - - - - - wmgmtt wbat default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0a0h: wnvdf wefr weds2 weds1 wevit weett wedat weht default 0 0 0 0 0 0 0 0 wan extract modes. this register determines which set of wan trap modes have been enabled. the wan trap modes can be unrelated to the lan trap modes in the opposi te direction. any combination of these traps can be enabled. if any enabled trap modes overlap so that the wa n trap indicates that a frame should be forwarded to an ethernet port and to the wan extract, the frame is to be only forwarded to the wan extract (e.g. the user might have configured the wan trap to forward the frame?s vlan id to ethernet port 1, but the frame?s da might also indicate that the frame is to be sent to the wan extr act). wan vlan/q-in-q forwarding is enabled through the forwarding mode (not through these registers). the default setting is all modes disabled. bit 9: wan extract management address trap (wmgmtt) 0 = wan extract management address trap is disabled. 1 = wan extract management address trap is enabled. all ethernet frames with an ethernet destination address (da) = 01:80:c2:xx:xx:xx, where ?x? is ?don?t care,? are forwarded to the wan extract queue. bit 8: wan extract broadcast address trap (wbat) 0 = wan extract broadcast address trap is disabled. 1 = wan extract broadcast address trap is enabled. all ethernet frames with an ethernet destination address (da) = ff:ff:ff:ff:ff:ff are fo rwarded to the wan extract queue. bit 7: wan ?no vlan/q-in-q? detected forwarding (wnvdf). 0 = when the 13 th and 14 th bytes in the frame do not equate to the va lue in wetpid, then the frame is to be forwarded to ethernet interface 1. 1 = when the 13 th and 14 th bytes in the frame do not equate to the va lue in wetpid, then the frame is to be forwarded to ethernet interface 2. to configure the x162 for vlan or q-in-q, wan to lan forwarding, the forwarding mode must be set to 5, and the wetpid register must be co nfigured (or use the configurat ion register default values). bit 6: wan extract fifo reset (wefr) 0 = normal ? no reset. 1 = one-time, momentary reset of the wan extract fifo.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 165 of 375 bits 4-5: wan extract decap source (weds[2:1]) 00 = wan extract is to be performed on the data st ream from decapsulator 1 (wan group 1). 01 = wan extract is to be performed on the data st ream from decapsulator 2 (wan group 2). 10 = wan extract is to be performed on the data st ream from decapsulator 3 (wan group 3). 11 = wan extract is to be performed on the data st ream from decapsulator 4 (wan group 4). note that not all decapsulators are available in all fo rwarding modes. the user should consult the forwarding diagrams in section 8.9.1 for the available decapsulators fo r the configured forwarding mode. bit 3: wan extract vlan id trap (wevit) 0 = wan extract vlan id trap is disabled. 1 = wan extract vlan id trap is enabled. (see section 8.16.2 for vlan table programming details.) note: invalid if the wan extract dec apsulator (selected by weds) has been configured to add an ethernet header (in pp.dmcr.dae[1:0]). adding an ethernet header implies that there is no vlan id to trap. bit 2: wan extract ethernet type trap (weett) 0 = wan extract ethernet type trap is disabled. 1 = wan extract ethernet type trap is enabled. note: invalid if the wan extract dec apsulator (selected by weds) has been configured to add an ethernet header (in pp.dmcr.dae[1:0]). adding an ethernet header implies t hat there is no ethernet type field to trap. note that wan extract ethernet type trapping is not available for fram e formats in which the ethernet type field is more than 32 bytes into the frame. thus, ethernet type trapping is not applicable on wan frames in the llc/snap frame format with 4/8 byte frame headers plus dual vlan tags. bit 1: wan extract destination address trap (wedat) 0 = wan extract destination address trap is disabled. 1 = wan extract destination address trap is enabled. note: invalid if the wan extract dec apsulator (selected by weds) has been configured to add an ethernet header (in pp.dmcr.dae[1:0]). adding an ethernet header im plies that there is no ethernet da to trap. bit 0: wan extract header trap (weht) 0 = wan extract header trap is disabled. 1 = wan extract header trap is enabled.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 166 of 375 register name: su.wehtp register description: wan extract header trap position register address: 0a2h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0a3h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0a2h: - - - wehth wehtl wehtp3 wehtp2 wehtp1 default 0 0 0 0 0 0 0 0 bit 4: wan extract header trap high byte (wehth). this value indicates whether the most significant byte of the weht is to be used when perf orming the wan extract header trap 0 = most significant byte is masked. 1 = most significant byte is tested (not masked). bit 3: wan extract header trap low byte (wehtl). this value indicates whether the least significant byte of the weht is to be used when perf orming the wan extract header trap 0 = least significant byte is masked. 1 = least significant byte is tested (not masked). bits 0-2: wan header extract trap position (wehtp[3:1]) this value indicates the beginning byte position within the wan frame, for where the wan header extract tr ap is to be tested. only binary values 0-6 are valid. a value ?0? indicates that the test is to begin on the firs t byte of the frame. the wan header trap enables trapping on slarp, gfp pti/upi, gfp cid or shim tag. example su.wehtp settings bytes tested wehth wehtl wehtp-3 we htp-2 wehtp-1 weht gfp ? pti management 1 1 0 0 0 0 100x xxxxb gfp linear -cid 1 1 0 1 0 0 xxh chdlc slarp 2 1 1 0 1 0 80 35h gfp null extension with tag-1 (shim; mpls-like) 2 1 1 1 0 0 xx xxh
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 167 of 375 register name: su.weht register description: wan extract header trap register address: 0a4h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0a5h: weht16 weht15 weht14 weht13 weht12 weht11 weht10 weht9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0a4h: weht8 weht7 weht6 weht5 weht4 weht3 weht2 weht1 default 0 0 0 0 0 0 0 0 bits 0-15: wan header trap (weht [16:1]) this value provides the first and second bytes of the wan header extract trap (least significant bytes of the trap he ader). any binary value is possible. the least significant of these two bytes is in bit positions 0 ? 7. register name: su.wedal register description: wan extract destination address low register address: 0a6h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0a7h: wedal16 wedal15 wedal14 wedal13 wedal12 wedal11 wedal10 wedal9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0a6h: wedal8 wedal7 wedal6 wedal5 wedal4 wedal3 wedal2 wedal1 default 0 0 0 0 0 0 0 0 bits 0-15: wan extract destin ation address low (wedal [16:1]) this value provides the first and second bytes of the wan extract destination a ddress (least significant bytes of the address). this value in combination with wedam and wedah make up the wan extract destinati on address. any binary value is possible. the least significant of these two bytes is in bit positions 0 ? 7. t he byte position of the da within the wan frame is derived from the decap, which knows whether 0, 4 or 8 wan header by tes will be removed. register name: su.wedam register description: wan extract destination address middle register address: 0a8h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0a9h: wedam16 wedam15 wedam14 wedam13 wedam12 wedam11 wedam10 wedam9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0a8h: wedam8 wedam7 wedam6 wedam5 wedam4 wedam3 wedam2 wedam1 default 0 0 0 0 0 0 0 0 bits 0-15: wan extract destinat ion address mid (wedam [16:1]) this value provides the third and fourth bytes of the wan extract destination address. this value in combination with wedal and wedah make up the wan extract destination address. any binary value is possibl e. the least significant of these two bytes is in bit positions 0 ? 7.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 168 of 375 register name: su.wedah register description: wan extract destination address high register address: 0aah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0abh: wedah16 wedah15 wedah14 wedah13 wedah12 wedah11 wedah10 wedah9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0aah: wedah8 wedah7 wedah6 wedah5 wedah4 wedah3 wedah2 wedah1 default 0 0 0 0 0 0 0 0 bits 0-15: wan extract destin ation address high (wedah [16:1]) this value provides the fifth and sixth bytes of the wan extract destination address. this value in combination with wedal and wedam make up the wan extract destination address. any binary value is possibl e. the least significant of these two bytes is in bit positions 0 ? 7. register name: su.wedax register description: wan extract destination address mask register address: 0ach bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0adh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0ach: wedax8 wedax7 wedax6 wedax5 wedax4 wedax3 wedax2 wedax1 default 0 0 0 0 0 0 0 0 bits 0-7: wan extract destination address mask (wedax [8:1]) this value provides a mask for the least significant byte of the wan extract de stination address (bits 0 - 7 of weda0) . this mask allows the device to trap on multiple das (e.g. bridge group address 01-80-c2-00-00-00, slow pr otocols 01-80-c2-00-00-01 and bridge management 01-80-c2-00-00-10). the default setting is all bit positions = 0. 0 = bit mask disabled. 1 = bit mask enabled (this bit of the wan extr act destination address is ?don?t care?).
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 169 of 375 register name: su.weet register description: wan extract ethernet type register address: 0aeh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0afh: weet16 weet15 weet14 weet13 weet12 weet11 weet10 weet9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0aeh: weet8 weet7 weet6 weet5 weet4 weet3 weet2 weet1 default 0 0 0 0 0 0 0 0 bits 0-15: wan extract ethernet type (weet [16:1]). this value defines the 2-byte ethernet protocol type that the wan trap is to monitor for. bits 0 to 7 are used to define the least significant byte. one example setting is 08-06 (hex) for ethernet type = arp. note that wan ex tract ethernet type trapping is not available for frame formats in which the ethernet type field is more than 32 bytes into the frame. thus, ethernet type trapping is not applicable on wan frames in the llc/snap frame format with 4/8 byte frame headers plus dual vlan tags. register name: su.wetpid register description: wan ethernet tag protocol id register address: 0b2h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0b3h: wetpid16 wetpid15 wetpid14 wetpid13 wetpid12 wetpid11 wetpid10 wetpid9 default 1 0 0 0 0 0 0 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0b2h: wetpid8 wetpid7 wetpid6 wetpid5 wetpid4 wetpid3 wetpid2 wetpid1 default 0 0 0 0 0 0 0 0 wan ethernet tag protocol id (wetpid [16:1]). this register specifies the ethernet tag protocol id that is used to denote wan-vlan frames. four example settings are 8100 (standard), 9100 and 9200 (juniper and foundry) and 88a8 (extreme). only applicable in forwarding mode 5.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 170 of 375 register name: su.wos register description: wan overflow status register address: 0b4h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0b5h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0b4h: - - - - - - - weos default 0 0 0 0 0 0 0 0 bit 0: wan extract overflow status 0 = no overflow events have oc curred since the last read. 1 = 1 or more overflow events have occurred since the last read.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 171 of 375 register name: su.lim register description: lan interface mode register address: 0b6h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0b7h: - - - - lp2r lp1r lp2ce lp1ce default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0b6h: - - - lifr liip2 liip1 lip lie default 0 0 0 0 0 0 0 0 bit 11: lan port #2 - sram queue reset (lp2r) 0 = normal operation. 1 = one-time, momentary reset of all sram queue po inters associated with lan transmit port 2. bit 10: lan port #1 - sram queue reset (lp1r) 0 = normal operation. 1 = one-time, momentary reset of all sram queue po inters associated with lan transmit port 1. to insure proper reset function, the associated mac tran smit must be disabled before a reset. this must be done to ensure that the transmit mac is not in the middle of transmitting a frame when the queue is reset. activating lp1r does not affect traffic on port 2 and acti vating lp2r does not affect traffic on port 1. bit 9: lan port 2 crc enable (lp2ce) 0 = the transmit mac will not add an ethernet fcs (crc) to frames before transmission. 1 = the transmit mac adds an ethernet fcs (crc) to all frames before transmission. bit 8: lan port 1 crc enable (lp1ce) 0 = the transmit mac will not add an ethernet fcs (crc) to frames before transmission. 1 = the transmit mac adds an ethernet fcs (crc) to all frames before transmission. bit 4: lan insert fifo reset (lifr) 0 = normal ? no reset. 1 = one-time, momentary reset of the lan insert fifo. bit 2-3: lan insert insertion point (liip[2:1]) 00 = lan insert data is multiplexed with data from decapsulator #1. 01 = lan insert data is multiplexed with data from decapsulator #2. 10 = lan insert data is multiplexed with data from decapsulator #3. 11 = lan insert data is multiplexed with data from decapsulator #4. if the lan insert is assigned to a decapsulator that is not enabled (because of the forwarding mode setting or because there are no enabled wan ports associated with that decapsulator) then the lan insert has exclusive use of that lan transmit queue. for mpl > 2048, if the lan insert is enabl ed (lie = 1), liip must equal 00. in forwarding modes 2 and 5, only liip = 00 and 10 are valid. in all other cases, the recommended value is liip = 01 for insertion to lan port 1, or liip = 10 for insertion to lan port 2. bit 1: lan insert priority (lip) 0 = lan insert frames are lower priority t han frames from the associated decapsulator. 1 = lan insert frames are higher priority t han frames from the associated decapsulator. bit 0: lan insert enable (lie) 0 = lan insertion is disabled. 1 = lan insertion is enabled.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 172 of 375 register name: su.wom register description: wan overflow mask register address: 0b8h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0b9h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0b8h: - - - - - - - weom default 0 0 0 0 0 0 0 0 bit 0: wan extract overflow interrupt mask 0 = weos will cause interrupts. 1 = weos will not cause interrupts.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 173 of 375 register name: su.lp1xs register description: lan port 1 transmit status register address: 0bah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0bbh: lted ltjto ltff - ltloc ltncp ltlc ltec default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0bah: - ltcc3 ltcc2 ltcc1 ltcc0 ltexd ltufe ltdef default 0 0 0 0 0 0 0 0 note: this is a real-time status register. usefulness is limited to single frame transmissions for system debugging. most applications will be better served by monitoring the mac management counter (mmc) registers rather than polling these bits. bit 15: lan transmit error detected (lted) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission attempt. indica tes jaber timeout, frame flushed, loss of carrier, no carrier, late collision, excessive collisions, or excessive deferral. bit 14: lan transmit jabber timeout (ltjto) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to jaber timeout. bit 13: lan transmit frame flushed (ltff) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to the frame being flushed by a software reset. bit 11: lan transmit loss of carrier (ltloc) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to loss of carrier. bit 10: lan transmit no carrier present (ltncp) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to the lack of a carrier. bit 9: lan transmit late collision (ltlc) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to a late collision. bit 8: lan transmit exce ssive collisions (ltec) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to excessive (>16) collisions. bits 3-6: lan transmit collision count (ltcc[3:0]) these real-time status bits indicate the number collisions encountered while attempting to transmit the current frame. bit 2: lan transmit excessive deferral (ltexd) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to excessive deferral. bit 1: lan transmit underflow error (ltufe) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to data underflow. bit 0: lan transmit deferred (ltdef) this real-time status bit is set to 1 when the transmit mac is deferring transmission due to carrier availability. only valid in half-duplex mode.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 174 of 375 register name: su.lp2xs register description: lan port 2 transmit status register address: 0bch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0bdh: lted ltjto ltff - ltloc ltncp ltlc ltec default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0bch: - ltcc3 ltcc2 ltcc1 ltcc0 ltexd ltufe ltdef default 0 0 0 0 0 0 0 0 note: this is a real-time status register. usefulness is limited to single frame transmissions for system debugging. most applications will be better served by monitoring the mac management counter (mmc) registers rather than polling these bits. bit 15: lan transmit error detected (lted) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission attempt. indica tes jaber timeout, frame flushed, loss of carrier, no carrier, late collision, excessive collisions, or excessive deferral. bit 14: lan transmit jabber timeout (ltjto) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to jaber timeout. bit 13: lan transmit frame flushed (ltff) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to the frame being flushed by a software reset. bit 11: lan transmit loss of carrier (ltloc) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to loss of carrier. bit 10: lan transmit no carrier present (ltncp) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to the lack of a carrier. bit 9: lan transmit late collision (ltlc) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to a late collision. bit 8: lan transmit exce ssive collisions (ltec) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to excessive (>16) collisions. bits 3-6: lan transmit collision count (ltcc[3:0]) these real-time status bits indicate the number collisions encountered while attempting to transmit the current frame. bit 2: lan transmit excessive deferral (ltexd) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to excessive deferral. bit 1: lan transmit underflow error (ltufe) this real-time status bit is set to 1 when the transmit mac encounters an error during a transmission due to data underflow. bit 0: lan transmit deferred (ltdef) this real-time status bit is set to 1 when the transmit mac is deferring transmission due to carrier availability. only valid in half-duplex mode.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 175 of 375 10.3.2 receive lan register definitions register name: su.lpm register description: lan port modes register address: 0c0h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0c1h: - - - - - - lmgmtt lbat default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0c0h: - - - leeps levit leett ledat lpm default 0 0 0 0 0 0 0 0 this register determines which set of lan trap mode s have been enabled and whether the device is being used in a single or dual lan port application. the lan trap modes can be unrelated to the wan trap modes in the opposite direction. any combination of these traps can be enabled. if any enabled trap modes overlap so that the lan trap indicates that a frame should be forwarded to a lan queue and to the lan extract, the frame is to be only forwarded to the lan extract (e.g. the user might have configured the lan trap to forward the frame?s vlan id to lan queue 1, but the frame?s da might also indicate that the frame is to be sent to the lan extract). lan vlan/q-in-q forwarding is enabled through the device?s forwarding mode (common control registers; not through these registers). bit 9: lan extract management address trap (lmgmtt) 0 = lan extract management address trap is disabled 1 = lan extract management address trap is enabled. all ethernet frames with an ethernet destination address (da) = 01:80:c2:xx:xx:xx, where ?x? is ?don?t care?, are fo rwarded to the lan extract queue. bit 8: lan extract broadcast address trap (lbat) 0 = lan extract broadcast a ddress trap is disabled 1 = lan extract broadcast address trap is enabled. all ethernet frames with an ethernet destination address (da) = ff:ff:ff:ff:ff:ff are fo rwarded to the lan extract queue. bit 4: lan extract lan port source (leeps) 0 = lan extract is to be performed on the data stream from lan port 1. 1 = lan extract is to be performed on the data stream from lan port 2. this option is only valid on devices that contain two ethernet ports, in forwarding modes 2, 4, and 5. bit 3: lan extract vlan id trap (levit) 0 = lan extract vlan id trap is disabled 1 = lan extract vlan id trap is enabled (see section 8.16.2 for vlan table programming details.) bit 2: lan extract ethernet type trap (leett) 0 = lan extract ethernet type trap is disabled 1 = lan extract ethernet type trap is enabled bit 1: lan extract destination address trap (ledat) 0 = lan extract destination address trap is disabled 1 = lan extract destinatio n address trap is enabled bit 0: lan port mode (lpm). 0 = single port applications using port 1 (required for gbe applications) 1 = dual port applications (gbe gmii operation not allowed)
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 176 of 375 register name: su.ledal register description: lan extract destination address low register address: 0c2h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0c3h: ledal15 ledal14 ledal13 ledal12 ledal11 ledal10 ledal9 ledal8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0c2h: ledal7 ledal6 ledal5 ledal4 ledal3 ledal2 ledal1 ledal0 default 0 0 0 0 0 0 0 0 bits 0-15: lan extract destination address low (ledal[16:1]). this value provides the first and second bytes of the lan extract destination addr ess (least significant bytes of the addre ss). this value in combination with ledam and ledah make up the lan extr act destination address. any binary value is possible. the least significant of these two bytes is in bit positions 0-7. register name: su.ledam register description: lan extract destination address middle register address: 0c4h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0c5h: ledam15 ledam14 ledam13 ledam12 ledam11 ledam10 ledam9 ledam8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0c4h: ledam7 ledam6 ledam5 ledam4 ledam3 ledam2 ledam1 ledam0 default 0 0 0 0 0 0 0 0 bits 0-15: lan extract destinat ion address middle (ledam[16:1]). this value provides the third and fourth bytes of the lan extract destination address. this value in combination with ledal and ledah make up the lan extract destination address. any binary value is possible. t he least significant of these two bytes is in bit positions 0-7.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 177 of 375 register name: su.ledah register description: lan extract destination address high register address: 0c6h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0c7h: ledah15 ledah14 ledah13 ledah12 ledah11 ledah10 ledah9 ledah8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0c6h: ledah7 ledah6 ledah5 ledah4 ledah3 ledah2 ledah1 ledah0 default 0 0 0 0 0 0 0 0 bits 0-15: lan extract destination address high (ledah[16:1]) this value provides the fifth and sixth bytes of the lan extract destination address. this value in combination with ledal and ledam make up the lan extract destination address. any binary value is possibl e. the least significant of these two bytes is in bit positions 0-7. register name: su.ledax register description: lan extract destination address mask register address: 0c8h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0c9h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0c8h: ledax7 ledax6 ledax5 ledax4 ledax3 ledax2 ledax1 ledax0 default 0 0 0 0 0 0 0 0 bits 0-7: lan extract destination address mask (ledax [8:1]). this value provides a mask for the least significant byte of the lan extract de stination address (bits 0 - 7 of leda0) . this mask allows the device to trap on multiple das (e.g. bridge group address 01-80-c2-00-00-00, slow pr otocols 01-80-c2-00-00-01 and bridge management 01-80-c2-00-00-10). 0 = bit mask disabled 1 = bit mask enabled (this bit of the lan extrac t destination address is ?does not care?)
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 178 of 375 register name: su.leet register description: lan extract ethernet type register address: 0cah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0cbh: leet15 leet14 leet13 leet12 leet11 leet10 leet9 leet8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0cah: leet7 leet6 leet5 leet4 leet3 leet2 leet1 leet0 default 0 0 0 0 0 0 0 0 bits 0-15: lan extract ethernet type (leet[16:1]). this value defines the 2-byte ethernet protocol type that the lan trap is to monitor for. bits 0 to 7 are used to define the least significant byte. one example setting is 08-06 (hex) for ethernet type = arp. register name: su.lp1c register description: lan port 1 control register address: 0cch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0cdh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0cch: lp1mim lp1qom lp1fr lp1pf2 lp1pf1 lp1etf2 lp1etf1 lp1e default 0 0 0 0 0 0 0 0 bit 7: lan port 1 mac interrupt mask control (lp1mim) 0 = interrupt is disabled so that la n port 1 mac cannot generate an interrupt. 1 = interrupt is enabled so that lan port 1 mac can generate an interrupt. bit 6: lan port 1 queue overflow mask (lp1qom) 0 = su.liqos.liqos1 will not generate an interrupt. 1 = su.liqos.liqos1 will generate an interrupt. bit 5: lan port 1 fifo reset (lp1fr) 0 = normal operation. 1 = reset the lan 1 receive fifo. the mac receiver should be disabled during fifo reset. bits 3-4: lan port 1 priority forwarding (lp1pf[2:1]) 00 = priority forwarding/scheduling disabled 01 = dscp (diffserv) priority forwarding/scheduling enabled 10 = 802.1q (vlan tag pcp) prio rity forwarding/scheduling enabled 11 = reserved bit 1-2: lan port 1 ethernet vlan tag function enab le(lp1etf[2:1]). the ethernet vlan tag functions are not required to be enabled for priority scheduling (lp1pf = 01/10). 00 = lan ethernet vlan tag functions disabled 01 = lan ethernet vlan tag extract, forwar ding/scheduling, discarding functions enabled 10 = reserved 11 = reserved bit 0: lan port 1 enable (lp1e) 0 = disabled 1 = enabled
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 179 of 375 register name: su.lp2c register description: lan port 2 control register address: 0ceh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0cfh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0ceh: lp2mim lp2qom lp2fr lp2pf2 lp2pf1 lp2etf2 lp2etf1 lp2e default 0 0 0 0 0 0 0 0 bit 7: lan port 2 mac interrupt mask control (lp2mim) 0 = interrupt is disabled so that la n port 2 mac cannot generate an interrupt. 1 = interrupt is enabled so that lan port 2 mac can generate an interrupt. bit 6: lan port 2 queue overflow mask (lp2qom) 0 = su.liqos.liqos2 will not generate an interrupt. 1 = su.liqos.liqos2 will generate an interrupt. bit 5: lan port 2 fifo reset (lp2fr) 0 = normal operation. 1 = reset the lan 2 receive fifo. the mac receiver should be disabled during fifo reset. bit 4-3: lan port 2 priority forwarding/scheduling (lp2pf[2:1]). 00 = priority forwarding/scheduling disabled 01 = dscp (diffserv) priority forwarding/scheduling enabled 10 = 802.1q (vlan tag pcp) prio rity forwarding/scheduling enabled 11 = reserved bit 2-1: lan port 2 ethernet vlan tag function enable (lp2etf[2:1]). the ethernet vlan tag functions are not required to be enabled for priority scheduling (lp1pf = 01/10). 00 = lan ethernet vlan tag functions disabled 01 = lan ethernet vlan tag extract, forwar ding/scheduling, discarding functions enabled 10 = reserved 11 = reserved bit 0: lan port 2 enable (lp2e). 0 = disabled 1 = enabled the l2pe = 1 (enabled) is only valid when lpm = 1 (dual port) and when in forwarding modes 2, 4, or 5. otherwise, the device should be configured to l2pe =0 (disabled). when lan port 2 priority forwarding or priority schedu ling has been enabled, the user must also configure the priority table and no priority detected registers. when lan port 2 ethernet tag forwarding has been enabled, the user must also configure the ethernet tag table and no ethernet tag detected registers.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 180 of 375 register name: su.lnfc register description: lan no-match forwarding control register address: 0d0h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0d1h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0d0h: - - lnpdf2 lnpdf1 lnetdf4 lnetdf3 lnetdf2 lnetdf1 default 0 0 0 0 0 0 0 0 bit 4-5: lan no priority tag detected forwarding (lnpdf[2:1]). enabled for each port with su.lp1c.lp1pf or su.lp2c.lp2pf . controls how frames are handled when the received frame does not contain dscp, does not contain a vlan tag, or the 13 th and 14 th bytes of the frame do not match the value in su.lqtpid . the same action is applied to both ethernet ports. 00 = forward to lan priority queue 1 01 = forward to lan priority queue 2 10 = forward to lan priority queue 3 11 = forward to lan priority queue 4 bit 0-3: lan no vlan tag detected forwarding (lnvdf[4:1]). enabled for each port with su.lp1c.lp1etf or su.lp2c.lp2etf . controls how frames are handled when the rece ived frame does not contain a vlan tag or the 13 th and 14 th bytes of the frame do no match the value in su.lqtpid . the same action is applied to both ethernet ports. 0000 = forward to wan group 1 0001 = forward to wan group 2 0010 = forward to wan group 3 0011 = forward to wan group 4 01xx = forward this frame to the lan extract queue 1xxx = discard this frame register name: su.lqxpc register description: lan queue watermark transmit pause control register address: 0d2h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0d3h: lqxpc16 lqxpc15 lqxpc 14 lqxpc13 lqxpc12 lqxp c11 lqxpc10 lqxpc9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0d2h: lqxpc8 lqxpc7 lqxpc6 lqxpc5 lqxpc4 lqxp c3 lqxpc2 lqxpc1 default 0 0 0 0 0 0 0 0 bits 0-15: lan queue watermark xmt pause control (lqxpc [16-1]) one bit is provided for each of the 16 lan queues. when set to one, a pause frame will be tr ansmitted when the associated queue has exceeded the watermark defined in ar.lqw . 0 = lan queue watermark xmt pause control disabled 1 = lan queue watermark xmt pause control enabled
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 181 of 375 register name: su.lqtpid register description: lan q-in-q and vlan tag protocol id register address: 0d4h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0d5h: lqtpid16 lqtpid15 lqtpid14 lqtpid13 lqtpid12 lqtpid11 lqtpid10 lqtpid9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0d4h: lqtpid8 lqtpid7 lqtpid6 lqtpid5 lqtpid4 lqtpid3 lqtpid2 lqtpid1 default 0 0 0 0 0 0 0 0 bits 0-15: lan q-in-q tag protocol id (lqtpid [16:1]) this register specifies the ethernet tag protocol id that is used to denote lan-vlan and q-in-q frames. fo ur example settings are 8100 (standard), 9100 and 9200 (juniper and foundry) and 88a8 (extre me). the default setting is for 8100. register name: su.liqos register description: lan port and lan queue overflow status register address: 0d6h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0d7h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0d6h: - - - - lp2i lp1i liqos2 liqos1 default 0 0 0 0 0 0 0 0 bit 3: lan port 2 interrupt status (lp2i): 0 = no active interrupt condition on lan port 2. 1 = active interrupt condition on lan port 2. reset following a read of this register. bit 2: lan port 1 interrupt status (lp1i): 0 = no active interrupt condition on lan port 1. 1 = active interrupt condition on lan port 1. reset following a read of this register. bit 1: lan input queue overflow status - lan port 2 (liqos2): 0 = no overflow events have oc curred since the last read 1 = 1 or more overflow events have occurred since the last read bit 0: lan input queue overflow status - lan port 1 (liqos1): 0 = no overflow events have oc curred since the last read 1 = 1 or more overflow events have occurred since the last read the lan queue overflow status register bits are se t when a frame has been discarded due to transmit lan queue overflow and are reset following a read of this register.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 182 of 375 register name: su.mpl register description: lan maximum packet length register address: 0d8h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0d9h: - - mpl14 mpl13 mpl12 mpl11 mpl10 mpl9 default 0 0 0 0 0 1 0 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0d8h: mpl8 mpl7 mpl6 mpl5 mpl4 mpl3 mpl2 mpl1 default 1 1 1 1 1 1 1 1 bits 0-13: maximum packet length (mpl [14:1]) maximum frame length, in bytes. the receive mac discards ethernet frame received from the lan interface that have a frame length greater than the user configured mpl value. this value is applied to both ethernet ports. if the device has been configured to discard the ethernet fcs then the byte count up to the fcs is used. if the fcs is re tained, then the count includes 4 bytes for the fcs. the maximum valid value for this register is 10240 byte s. note that frames between 9018 and 10240 bytes may be counted as ?giant frames? by the mac. table 10-5. valid conditions for mpl > 2048 description register / bit jumbo frames supported when comments forwarding mode gl.cr1 . fmc = 001 forwarding mode 2 only. priority scheduling ar.lqsc.lqsm = 0 only no priority or strict priority scheduling supported. lan port mode su.lpm.lpm = 0 for dual port devices, single port mode must be used. lan port 2 enable su.lp2c.lp2e = 0 for dual port devices, port 2 must be disabled. port 1 policing su.l1pp.l1pm[2:1] = 00 port policing must be disabled. bridge filter su.bfc.bfe = 0 bridge filter must be disabled. lan insert su.lim.liip[2:1] = 00 if lan insert is enabled. lan extract su.lpm.leeps = 0 if lan extract is enabled (lpm enables).
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 183 of 375 register name: su.l1pp register description: lan 1 policing parameters register address: 0dah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0dbh: cbss - - - l1pm2 l1pm1 l1pcr2 l1pcr1 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0dah: l1pct8 l1pct7 l1pct6 l1pct5 l1pct4 l1pct3 l1pct2 l1pct1 default 0 0 0 0 0 0 0 0 lan 1 policing parameters . this register determines the policing function setting for ethernet port 1. the policing function is used to control the rate at which fram es are forwarded to serial interfaces. the policing function can be configured to send explicit back pressure flow control to the ethernet sendi ng equipment (ethernet pause control) or can be used to enable a frame discarding mechanism that restrict the rate at which frame are accepted. bit 15: committed burst size selection (cbss) this bit function is not available in device revision a1 ( gl.idr.revn = 000). 0 = default condition. cbs is 4096 bytes. 1 = cbs is 12288 bytes. only valid in policing discard mode. bits 10-11: lan 1 policing mode (l1pm[2:1]) 00 = policing disabled 01 = policing pause enabled 10 = policing discard enabled 11 = reserved bits 8-9: lan 1 policing credit range (l1pcr[2:1]) 00 = low credit range for cir = 64kbps to 2mbps 01 = mid credit range for cir = 2mbps to 16mbps 10 = high credit range for cir = 16mbps to 416mbps 11 = reserved bits 0-7: lan 1 policing cred it threshold (l1pct[8:1]). this register specifies the credit threshold setting of the policing function. only values between 8 to 255 are supported.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 184 of 375 register name: su.l2pp register description: lan 2 policing parameters register address: 0dch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0ddh: cbss - - - l2pm2 l2pm1 l2pcr2 l2pcr1 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0dch: l2pct8 l2pct7 l2pct6 l2pct5 l2pct4 l2pct3 l2pct2 l2pct1 default 0 0 0 0 0 0 0 0 lan 2 policing parameters. this register determines the policing functi on setting for ethernet port 2. the policing function is used to control the rate at which frames are fo rwarded to serial interfaces. the policing function can be configured to send explicit back pressure flow c ontrol to the ethernet sending equipment (ethernet pause control) or can be used to enable a frame discarding mechanism that restrict the rate at which frame are accepted. bit 15: committed burst size selection (cbss) this bit function is not available in device revision a1 ( gl.idr.revn=000). 0 = default condition. cbs is 4096 bytes. 1 = cbs is 12288 bytes. only valid in policing discard mode. bits 10-11: lan 2 policing mode (l2pm[2:1]) 00 = policing disabled 01 = policing pause enabled 10 = policing discard enabled 11 = reserved bits 8-9: lan 2 policing credit range (l2pcr[2:1]) 00 = low credit range for cir = 64kbps to 2mbps 01 = mid credit range for cir = 2mbps to 16mbps 10 = high credit range for cir = 16mbps to 416mbps 11 = reserved bits 0-7: lan 2 policing cred it threshold (l2pct[8:1]). this register specifies the credit threshold setting of the policing function. only values between 8 to 255 are supported.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 185 of 375 register name: su.ptc register description: priority table control register address: 0deh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0dfh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0deh: - - - - - - pte ptaim default 0 0 0 0 0 0 0 0 priority table control this register is used to initialize and specify the operating mode of the priority table. the initialization function causes each entry of the priority table to be populated with the priority table write data default value. the configuration of this table is similar to that of the vlan table. however, although this table provides an automated self-init at power-up, it does not a llow the user to request a new initialization ?at will?. bit 1: priority table enable (pte) when equal to zero, the priority table is enabled. when set to 1, the priority table does not affect the forwarding of frames. bit 0: priority table auto increment mode (ptaim) when set, the priority table address in su.ptaa is automatically with each read or write of the su.ptwd or su.ptrd registers.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 186 of 375 register name: su.ptaa register description: priority table access address register address: 0e0h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0e1h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0e0h: - ptpaa ptaa6 ptaa5 ptaa4 ptaa3 ptaa2 ptaa1 default 0 0 0 0 0 0 0 0 bit 6: priority table port access address (ptpaa). this bit is an extension of the ptaa[6:1] bits, but is used to divide between priority lookups for et hernet (lan) port 1 (ptpaa = 0) and et hernet (lan) port 2 (ptpaa = 1). not valid for devices with only one ethernet port. bits 0-5: priority table access address (ptaa [6:1]). these bits provide the priority table address for a up read or write operation. the address into the priority t able is used to resolve vlan 802.1p pcp and dscp to the four priority levels. when using pcp priority mode, onl y addresses ptaa[3:1] are used. the priority mode for each ethernet port can be independently selected using the su.lp1c and su.lp2c registers. register name: su.ptwd register description: priority table write data register address: 0e2h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0e3h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0e2h: - - - - - - lpqfw2 lpqfw1 default 0 0 0 0 0 0 0 0 bits 0-1: lan priority queue forwarding (lpqfw[2:1]) 00 = map the value of this table entry?s addr ess (pcp or dscp) to priority level 1 01 = map the value of this table entry?s addr ess (pcp or dscp) to priority level 2 10 = map the value of this table entry?s addr ess (pcp or dscp) to priority level 3 11 = map the value of this table entry?s addr ess (pcp or dscp) to priority level 4
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 187 of 375 register name: su.ptrd register description: priority table read data register address: 0e4h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0e5h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0e4h: - - - - - - lpqfr2 lpqfr1 default 0 0 0 0 0 0 0 0 bits 0-1: lan priority queue forwarding (lpqfr[2:1]) 00 = the value of this table entry?s address (p cp or dscp) is mapped to priority level 1 01 = the value of this table entry?s address (p cp or dscp) is mapped to priority level 2 10 = the value of this table entry?s address (p cp or dscp) is mapped to priority level 3 11 = the value of this table entry?s address (p cp or dscp) is mapped to priority level 4 note that lan-vlan discarding and lan extraction takes precedence over priority forwarding. register name: su.ptsa register description: priority table shadow address register address: 0e6h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0e7h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0e6h: ptis ptpsa ptsa6 ptsa5 ptsa4 ptsa3 ptsa2 ptsa1 default 0 0 0 0 0 0 0 0 bit 7: priority table initialization status (ptis): this bit is set when the priority table initialization has been completed. bit 6: priority table port shadow address (ptsaa). this bit is an extension of the ptsa [6:1] bits, but is used to divide between priority lookups for lan port 1 (ptsaa = 0) and lan port 2 (ptsaa = 1). bits 0-5: priority table shadow address (ptsa [6:1]). this register interfaces directly to the priority table memory block to provide the selected priority table addr ess that is to be used for each priority table operation (lan trap, wan trap or up read/write). when ptaim = 1, the shadow address aut omatically increments for each updated read and/or write pr iority table access address.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 188 of 375 10.3.3 bridge filter registers register name: su.bfc register description: bridge filter control register address: 0e8h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0e9h: - - - - - bftr bfe bfap9 default 0 0 0 0 0 0 0 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0e8h: bfap8 bfap7 bfap6 bfap5 bfap4 bfap3 bfap2 bfap1 default 0 0 1 0 1 1 0 0 bit 10: bridge filter table reset (bftr). when the user configures this bit to bftr = 1, the bridge filter automatically steps through each of the 4096 bridge filter table addresses, aging all table entries so that the table is reset (one-time event each time the user writes bftr = 1). 0 = no bridge filter table reset 1 = one-time bridge filter table reset bit 9: automatic bridge filter enable (bfe) 0 = automatic bridging and filtering disabled for all ethernet ports. 1 = automatic bridging and filtering enabled for all ethernet ports. bits 8-0: bridge filter aging period (bfap[1-9]). these bits provide the binary coded value for the aging period. the valid equivalent decimal values for this variable are 1 to 300. values larger than 300 will not increase the aging period above 300 seconds. the default is set to 300 sec.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 189 of 375 10.4 arbiter registers the arbiter manages the transport between the ethernet port and the serial inte rface. it is responsible for queuing and dequeuing data to an external sdram. the arbiter handl es requests from the hdlc and mac to transfer data to/from the sdram. 10.4.1 arbiter register bit descriptions register name: ar.lq1sa register description: lan queue 1 start address register address: 100h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 101h: - - - - - lq1qpr lq1sa-10 lq1sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 100h: lq1sa-8 lq1sa-7 lq1sa-6 lq1sa-5 lq1sa-4 lq1sa-3 lq1sa-2 lq1sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 1 queue pointer reset 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 1 start address [10-1] this register specifies the start address for the lan queue 1. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq2sa register description: lan queue 2 start address register address: 102h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 103h: - - - - - lq2qpr lq2sa-10 lq2sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 102h: lq2sa-8 lq2sa-7 lq2sa-6 lq2sa-5 lq2sa-4 lq2sa-3 lq2sa-2 lq2sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 2 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 2 start address [10-1] this register specifies the start address for the lan queue 2. the value specifies the most significant 10 bits of the sdram absolute address.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 190 of 375 register name: ar.lq3sa register description: lan queue 3 start address register address: 104h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 105h: - - - - - lq3qpr lq3sa-10 lq3sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 104h: lq3sa-8 lq3sa-7 lq3sa-6 lq3sa-5 lq3sa-4 lq3sa-3 lq3sa-2 lq3sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 3 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 3 start address [10-1] this register specifies the start address for the lan queue 3. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq4sa register description: lan queue 4 start address register address: 106h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 107h: - - - - - lq4qpr lq4sa-10 lq4sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 106h: lq4sa-8 lq4sa-7 lq4sa-6 lq4sa-5 lq4sa-4 lq4sa-3 lq4sa-2 lq4sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 4 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 4 start address [10-1] this register specifies the start address for the lan queue 4. the value specifies the most significant 10 bits of the sdram absolute address.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 191 of 375 register name: ar.lq5sa register description: lan queue 5 start address register address: 108h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 109h: - - - - - lq5qpr lq5sa-10 lq5sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 108h: lq5sa-8 lq5sa-7 lq5sa-6 lq5sa-5 lq5sa-4 lq5sa-3 lq5sa-2 lq5sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 5 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 5 start address [10-1] this register specifies the start address for the lan queue 5. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq6sa register description: lan queue 6 start address register address: 10ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 10bh: - - - - - lq6qpr lq6sa-10 lq6sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10ah: lq6sa-8 lq6sa-7 lq6sa-6 lq6sa-5 lq6sa-4 lq6sa-3 lq6sa-2 lq6sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 6 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 6 start address [10-1] this register specifies the start address for the lan queue 6. the value specifies the most significant 10 bits of the sdram absolute address.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 192 of 375 register name: ar.lq7sa register description: lan queue 7 start address register address: 10ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 10dh: - - - - - lq7qpr lq7sa-10 lq7sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10ch: lq7sa-8 lq7sa-7 lq7sa-6 lq7sa-5 lq7sa-4 lq7sa-3 lq7sa-2 lq7sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 7 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 7 start address [10-1] this register specifies the start address for the lan queue 7. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq8sa register description: lan queue 8 start address register address: 10eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 10fh: - - - - - lq8qpr lq8sa-10 lq8sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10eh: lq8sa-8 lq8sa-7 lq8sa-6 lq8sa-5 lq8sa-4 lq8sa-3 lq8sa-2 lq8sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 8 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 8 start address [10-1]. this register specifies the start address for the lan queue 8. the value specifies the most significant 10 bits of the sdram absolute address.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 193 of 375 register name: ar.lq9sa register description: lan queue 9 start address register address: 110h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 111h: - - - - - lq9qpr lq9sa-10 lq9sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 110h: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default 0 0 0 0 0 0 0 0 bit 10: lan queue 9 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 9 start address [10-1]. this register specifies the start address for the lan queue 9. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq10sa register description: lan queue 10 start address register address: 112h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 113h: - - - - - lq10qpr lq10sa-10 lq10sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 112h: lq10sa-8 lq10sa-7 lq10sa-6 lq10sa-5 lq10sa-4 lq10sa-3 lq10sa-2 lq10sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 10 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 10 start address [10-1] this register specifies the star t address for the lan queue 10. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 194 of 375 register name: ar.lq11sa register description: lan queue 11 start address register address: 114h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 115h: - - - - - lq11qpr lq11sa-10 lq11sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 114h: lq11sa-8 lq11sa-7 lq11sa-6 lq11sa-5 lq11sa-4 lq11sa-3 lq11sa-2 lq11sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 11 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 11 start address [10-1]. this register specifies the star t address for the lan queue 11. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.lq12sa register description: lan queue 12 start address register address: 116h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 117h: - - - - - lq12qpr lq12sa-10 lq12sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 116h: lq12sa-8 lq12sa-7 lq12sa-6 lq12sa-5 lq12sa-4 lq12sa-3 lq12sa-2 lq12sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 12 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 12 start address [10-1] this register specifies the star t address for the lan queue 12. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 195 of 375 register name: ar.lq13sa register description: lan queue 13 start address register address: 118h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 119h: - - - - - lq13qpr lq13sa-10 lq13sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 118h: lq13sa-8 lq13sa-7 lq13sa-6 lq13sa-5 lq13sa-4 lq13sa-3 lq13sa-2 lq13sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 13 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 13 start address [10-1] this register specifies the star t address for the lan queue 13. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.lq14sa register description: lan queue 14 start address register address: 11ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 11bh: - - - - - lq14qpr lq14sa-10 lq14sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11ah: lq14sa-8 lq14sa-7 lq14sa-6 lq14sa-5 lq14sa-4 lq14sa-3 lq14sa-2 lq14sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 14 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 14 start address [10-1] this register specifies the star t address for the lan queue 14. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 196 of 375 register name: ar.lq15sa register description: lan queue 15 start address register address: 11ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 11dh: - - - - - lq15qpr lq15sa-10 lq15sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11ch: lq15sa-8 lq15sa-7 lq15sa-6 lq15sa-5 lq15sa-4 lq15sa-3 lq15sa-2 lq15sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 15 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 15 start address [10-1]. this register specifies the star t address for the lan queue 15. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.lq16sa register description: lan queue 16 start address register address: 11eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 11fh: - - - - - lq16qpr lq16sa-10 lq16sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11eh: lq16sa-8 lq16sa-7 lq16sa-6 lq16sa-5 lq16sa-4 lq16sa-3 lq16sa-2 lq16sa-1 default 0 0 0 0 0 0 0 0 bit 10: lan queue 16 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan queue 16 start address [10-1]. this register specifies the star t address for the lan queue 16. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 197 of 375 register name: ar.lq1ea register description: lan queue 1 end address register address: 120h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 121h: - - - - - - lq1ea-10 lq1ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 120h: lq1ea-8 lq1ea-7 lq1ea-6 lq1ea-5 lq1ea-4 lq1ea-3 lq1ea-2 lq1ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 1 end address [10-1] this register specifies the end address for the lan queue 1. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq2ea register description: lan queue 2 end address register address: 122h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 123h: - - - - - - lq2ea-10 lq2ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 122h: lq2ea-8 lq2ea-7 lq2ea-6 lq2ea-5 lq2ea-4 lq2ea-3 lq2ea-2 lq2ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 2 end address [10-1] this register specifies the end address for the lan queue 2. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq3ea register description: lan queue 3 end address register address: 124h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 125h: - - - - - - lq3ea-10 lq3ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 124h: lq3ea-8 lq3ea-7 lq3ea-6 lq3ea-5 lq3ea-4 lq3ea-3 lq3ea-2 lq3ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 3 end address [10-1]. this register specifies the end address for the lan queue 3. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq4ea register description: lan queue 4 end address register address: 126h
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 198 of 375 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 127h: - - - - - - lq4ea-10 lq4ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 126h: lq4ea-8 lq4ea-7 lq4ea-6 lq4ea-5 lq4ea-4 lq4ea-3 lq4ea-2 lq4ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 4 end address [10-1] this register specifies the end address for the lan queue 4. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq5ea register description: lan queue 5 end address register address: 128h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 129h: - - - - - - lq5ea-10 lq5ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 128h: lq5ea-8 lq5ea-7 lq5ea-6 lq5ea-5 lq5ea-4 lq5ea-3 lq5ea-2 lq5ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 5 end address [10-1] this register specifies the end address for the lan queue 5. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq6ea register description: lan queue 6 end address register address: 12ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 12bh: - - - - - - lq6ea-10 lq6ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12ah: lq6ea-8 lq6ea-7 lq6ea-6 lq6ea-5 lq6ea-4 lq6ea-3 lq6ea-2 lq6ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 6 end address [10-1] this register specifies the end address for the lan queue 6. the value specifies the most significant 10 bits of the sdram absolute address.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 199 of 375 register name: ar.lq7ea register description: lan queue 7 end address register address: 12ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 12dh: - - - - - - lq7ea-10 lq7ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12ch: lq7ea-8 lq7ea-7 lq7ea-6 lq7ea-5 lq7ea-4 lq7ea-3 lq7ea-2 lq7ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 7 end address [10-1] this register specifies the end address for the lan queue 7. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq8ea register description: lan queue 8 end address register address: 12eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 12fh: - - - - - - lq8ea-10 lq8ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12eh: lq8ea-8 lq8ea-7 lq8ea-6 lq8ea-5 lq8ea-4 lq8ea-3 lq8ea-2 lq8ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 8 end address [10-1] this register specifies the end address for the lan queue 8. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.lq9ea register description: lan queue 9 end address register address: 130h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 131h: - - - - - - lq9ea-10 lq9ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 130h: lq9ea-8 lq9ea-7 lq9ea-6 lq9ea-5 lq9ea-4 lq9ea-3 lq9ea-2 lq9ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 9 end address [10-1] this register specifies the end address for the lan queue 9. the value specifies the most significant 10 bits of the sdram absolute address.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 200 of 375 register name: ar.lq10ea register description: lan queue 10 end address register address: 132h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 133h: - - - - - - lq10ea-10 lq10ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 132h: lq10ea-8 lq10ea-7 lq10ea-6 lq10ea-5 lq10ea-4 lq10ea-3 lq10ea-2 lq10ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 10 end address [10-1]. this register specifies the end address for the lan queue 10. the value specifies the most significant 10 bits of the s dram absolute address, result ing in a granularity of 32,768 bytes per lsb. register name: ar.lq11ea register description: lan queue 11 end address register address: 134h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 135h: - - - - - - lq11ea-10 lq11ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 134h: lq11ea-8 lq11ea-7 lq11ea-6 lq11ea-5 lq11ea-4 lq11ea-3 lq11ea-2 lq11ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 11 end address [10-1] this register specifies the end address for the lan queue 11. the value specifies the most significant 10 bits of the s dram absolute address, result ing in a granularity of 32,768 bytes per lsb. register name: ar.lq12ea register description: lan queue 12 end address register address: 136h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 137h: - - - - - - lq12ea-10 lq12ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 136h: lq12ea-8 lq12ea-7 lq12ea-6 lq12ea-5 lq12ea-4 lq12ea-3 lq12ea-2 lq12ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 12 end address [10-1] this register specifies the end address for the lan queue 12. the value specifies the most significant 10 bits of the s dram absolute address, result ing in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 201 of 375 register name: ar.lq13ea register description: lan queue 13 end address register address: 138h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 139h: - - - - - - lq13ea-10 lq13ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 138h: lq13ea-8 lq13ea-7 lq13ea-6 lq13ea-5 lq13ea-4 lq13ea-3 lq13ea-2 lq13ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 13 end address [10-1] this register specifies the end address for the lan queue 13. the value specifies the most significant 10 bits of the s dram absolute address, result ing in a granularity of 32,768 bytes per lsb. register name: ar.lq14ea register description: lan queue 14 end address register address: 13ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 13bh: - - - - - - lq14ea-10 lq14ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 13ah: lq14ea-8 lq14ea-7 lq14ea-6 lq14ea-5 lq14ea-4 lq14ea-3 lq14ea-2 lq14ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 14 end address [10-1] this register specifies the end address for the lan queue 14. the value specifies the most significant 10 bits of the s dram absolute address, result ing in a granularity of 32,768 bytes per lsb. register name: ar.lq15ea register description: lan queue 15 end address register address: 13ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 13dh: - - - - - - lq15ea-10 lq15ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 13ch: lq15ea-8 lq15ea-7 lq15ea-6 lq15ea-5 lq15ea-4 lq15ea-3 lq15ea-2 lq15ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 15 end address [10-1] this register specifies the end address for the lan queue 15. the value specifies the most significant 10 bits of the s dram absolute address, result ing in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 202 of 375 register name: ar.lq16ea register description: lan queue 16 end address register address: 13eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 13fh: - - - - - - lq16ea-10 lq16ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 13eh: lq16ea-8 lq16ea-7 lq16ea-6 lq16ea-5 lq16ea-4 lq16ea-3 lq16ea-2 lq16ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan queue 16 end address [10-1]. this register specifies the end address for the lan queue 16. the value specifies the most significant 10 bits of the s dram absolute address, result ing in a granularity of 32,768 bytes per lsb. register name: ar.wq1sa register description: wan queue 1 start address register address: 140h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 141h: - - - - - wq1qpr wq1sa-10 wq1sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 140h: wq1sa-8 wq1sa-7 wq1sa-6 wq1sa-5 wq1sa-4 wq1sa-3 wq1sa-2 wq1sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 1 queue pointer reset 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 1 start address [10-1] this register specifies the star t address for the wan queue 1. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 203 of 375 register name: ar.wq2sa register description: wan queue 2 start address register address: 142h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 143h: - - - - - wq2qpr wq2sa-10 wq2sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 142h: wq2sa-8 wq2sa-7 wq2sa-6 wq2sa-5 wq2sa-4 wq2sa-3 wq2sa-2 wq2sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 2 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 2 start address [10-1] this register specifies the star t address for the wan queue 2. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq3sa register description: wan queue 3 start address register address: 144h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 145h: - - - - - wq3qpr wq3sa-10 wq3sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 144h: wq3sa-8 wq3sa-7 wq3sa-6 wq3sa-5 wq3sa-4 wq3sa-3 wq3sa-2 wq3sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 3 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 3 start address [10-1]. this register specifies the star t address for the wan queue 3. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 204 of 375 register name: ar.wq4sa register description: wan queue 4 start address register address: 146h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 147h: - - - - - wq4qpr wq4sa-10 wq4sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 146h: wq4sa-8 wq4sa-7 wq4sa-6 wq4sa-5 wq4sa-4 wq4sa-3 wq4sa-2 wq4sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 4 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 4 start address [10-1] this register specifies the star t address for the wan queue 4. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq5sa register description: wan queue 5 start address register address: 148h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 149h: - - - - - wq5qpr wq5sa-10 wq5sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 148h: wq5sa-8 wq5sa-7 wq5sa-6 wq5sa-5 wq5sa-4 wq5sa-3 wq5sa-2 wq5sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 5 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 5 start address [10-1] this register specifies the star t address for the wan queue 5. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 205 of 375 register name: ar.wq6sa register description: wan queue 6 start address register address: 14ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 14bh: - - - - - wq6qpr wq6sa-10 wq6sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 14ah: wq6sa-8 wq6sa-7 wq6sa-6 wq6sa-5 wq6sa-4 wq6sa-3 wq6sa-2 wq6sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 6 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 6 start address [10-1] this register specifies the star t address for the wan queue 6. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq7sa register description: wan queue 7 start address register address: 14ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 14dh: - - - - - wq7qpr wq7sa-10 wq7sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 14ch: wq7sa-8 wq7sa-7 wq7sa-6 wq7sa-5 wq7sa-4 wq7sa-3 wq7sa-2 wq7sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 7 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 7 start address [10-1] this register specifies the star t address for the wan queue 7. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 206 of 375 register name: ar.wq8sa register description: wan queue 8 start address register address: 14eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 14fh: - - - - - wq8qpr wq8sa-10 wq8sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 14eh: wq8sa-8 wq8sa-7 wq8sa-6 wq8sa-5 wq8sa-4 wq8sa-3 wq8sa-2 wq8sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 8 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 8 start address [10-1]. this register specifies the star t address for the wan queue 8. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq9sa register description: wan queue 9 start address register address: 150h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 151h: - - - - - wq9qpr wq9sa-10 wq9sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 150h: wq9sa-8 wq9sa-7 wq9sa-6 wq9sa-5 wq9sa-4 wq9sa-3 wq9sa-2 wq9sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 9 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 9 start address [10-1] this register specifies the star t address for the wan queue 9. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 207 of 375 register name: ar.wq10sa register description: wan queue 10 start address register address: 152h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 153h: - - - - - wq10qpr wq10sa-10 wq10sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 152h: wq10sa-8 wq10sa-7 wq10sa-6 wq10sa-5 wq10sa-4 wq10sa-3 wq10sa-2 wq10sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 10 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 10 start address [10-1]. this register specifies the start address for the wan queue 10. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq11sa register description: wan queue 1 1start address register address: 154h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 155h: - - - - - wq11qpr wq11sa-10 wq11sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 154h: wq11sa-8 wq11sa-7 wq11sa-6 wq11sa-5 wq11sa-4 wq11sa-3 wq11sa-2 wq11sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 11 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 11 start address [10-1] this register specifies the start address for the wan queue 11. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 208 of 375 register name: ar.wq12sa register description: wan queue 12 start address register address: 156h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 157h: - - - - - wq12qpr wq12sa-10 wq12sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 156h: wq12sa-8 wq12sa-7 wq12sa-6 wq12sa-5 wq12sa-4 wq12sa-3 wq12sa-2 wq12sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 12 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 12 start address [10-1]. this register specifies the start address for the wan queue 12. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq13sa register description: wan queue 13 start address register address: 158h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 159h: - - - - - wq13qpr wq13sa-10 wq13sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 158h: wq13sa-8 wq13sa-7 wq13sa-6 wq13sa-5 wq13sa-4 wq13sa-3 wq13sa-2 wq13sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 13 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 13 start address [10-1] this register specifies the start address for the wan queue 13. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 209 of 375 register name: ar.wq14sa register description: wan queue 14 start address register address: 15ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 15bh: - - - - - wq14qpr wq14sa-10 wq14sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 15ah: wq14sa-8 wq14sa-7 wq14sa-6 wq14sa-5 wq14sa-4 wq14sa-3 wq14sa-2 wq14sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 14 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 14 start address [10-1] this register specifies the start address for the wan queue 14. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq15sa register description: wan queue 15 start address register address: 15ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 15dh: - - - - - wq15qpr wq15sa-10 wq15sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 15ch: wq15sa-8 wq15sa-7 wq15sa-6 wq15sa-5 wq15sa-4 wq15sa-3 wq15sa-2 wq15sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 15 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 15 start address [10-1] this register specifies the start address for the wan queue 15. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 210 of 375 register name: ar.wq16sa register description: wan queue 16 start address register address: 15eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 15fh: - - - - - wq16qpr wq16sa-10 wq16sa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 15eh: wq16sa-8 wq16sa-7 wq16sa-6 wq16sa-5 wq16sa-4 wq16sa-3 wq16sa-2 wq16sa-1 default 0 0 0 0 0 0 0 0 bit 10: wan queue 16 queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan queue 16 start address [10-1] this register specifies the start address for the wan queue 16. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq1ea register description: wan queue 1 end address register address: 160h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 161h: - - - - - - wq1ea-10 wq1ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 160h: wq1ea-8 wq1ea-7 wq1ea-6 wq1ea-5 wq1ea-4 wq1ea-3 wq1ea-2 wq1ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 1 end address [10-1] this register specifies the end address for the wan queue 1. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.wq2ea register description: wan queue 2 end address register address: 162h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 163h: - - - - - - wq2ea-10 wq2ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 162h: wq2ea-8 wq2ea-7 wq2ea-6 wq2ea-5 wq2ea-4 wq2ea-3 wq2ea-2 wq2ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 2 end address [10-1] this register specifies the end address for the wan queue 2. the value specifies the most significant 10 bits of the sdram absolute address.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 211 of 375 register name: ar.wq3ea register description: wan queue 3 end address register address: 164h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 165h: - - - - - - wq3ea-10 wq3ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 164h: wq3ea-8 wq3ea-7 wq3ea-6 wq3ea-5 wq3ea-4 wq3ea-3 wq3ea-2 wq3ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 3 end address [10-1] this register specifies the end address for the wan queue 3. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.wq4ea register description: wan queue 4 end address register address: 166h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 167h: - - - - - - wq4ea-10 wq4ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 166h: wq4ea-8 wq4ea-7 wq4ea-6 wq4ea-5 wq4ea-4 wq4ea-3 wq4ea-2 wq4ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 4 end address [10-1] this register specifies the end address for the wan queue 4. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.wq5ea register description: wan queue 5 end address register address: 168h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 169h: - - - - - - wq5ea-10 wq5ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 168h: wq5ea-8 wq5ea-7 wq5ea-6 wq5ea-5 wq5ea-4 wq5ea-3 wq5ea-2 wq5ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 5 end address [10-1] this register specifies the end address for the wan queue 5. the value specifies the most significant 10 bits of the sdram absolute address.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 212 of 375 register name: ar.wq6ea register description: wan queue 6 end address register address: 16ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 16bh: - - - - - - wq6ea-10 wq6ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16ah: wq6ea-8 wq6ea-7 wq6ea-6 wq6ea-5 wq6ea-4 wq6ea-3 wq6ea-2 wq6ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 6 end address [10-1] this register specifies the end address for the wan queue 6. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.wq7ea register description: wan queue 7 end address register address: 16ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 16dh: - - - - - - wq7ea-10 wq7ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16ch: wq7ea-8 wq7ea-7 wq7ea-6 wq7ea-5 wq7ea-4 wq7ea-3 wq7ea-2 wq7ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 7 end address [10-1] this register specifies the end address for the wan queue 7. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.wq8ea register description: wan queue 8 end address register address: 16eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 16fh: - - - - - - wq8ea-10 wq8ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16eh: wq8ea-8 wq8ea-7 wq8ea-6 wq8ea-5 wq8ea-4 wq8ea-3 wq8ea-2 wq8ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 8 end address [10-1] this register specifies the end address for the wan queue 8. the value specifies the most significant 10 bits of the sdram absolute address.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 213 of 375 register name: ar.wq9ea register description: wan queue 9 end address register address: 170h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 171h: - - - - - - wq9ea-10 wq9ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 170h: wq9ea-8 wq9ea-7 wq9ea-6 wq9ea-5 wq9ea-4 wq9ea-3 wq9ea-2 wq9ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 9 end address [10-1] this register specifies the end address for the wan queue 9. the value specifies the most significant 10 bits of the sdram absolute address. register name: ar.wq10ea register description: wan queue 10 end address register address: 172h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 173h: - - - - - - wq10ea-10 wq10ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 172h: wq10ea-8 wq10ea-7 wq10ea-6 wq10ea-5 wq10ea-4 wq10ea-3 wq10ea-2 wq10ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 10 end address [10-1] this register specifies the end address for the wan queue 10. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq11ea register description: wan queue 11 end address register address: 174h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 175h: - - - - - - wq11ea-10 wq11ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 174h: wq11ea-8 wq11ea-7 wq11ea-6 wq11ea-5 wq11ea-4 wq11ea-3 wq11ea-2 wq11ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 11 end address [10-1] this register specifies the end address for the wan queue 11. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 214 of 375 register name: ar.wq12ea register description: wan queue 12 end address register address: 176h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 177h: - - - - - - wq12ea-10 wq12ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 176h: wq12ea-8 wq12ea-7 wq12ea-6 wq12ea-5 wq12ea-4 wq12ea-3 wq12ea-2 wq12ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 12 end address [10-1]. this register specifies the e nd address for the wan queue 12. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq13ea register description: wan queue 13 end address register address: 178h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 179h: - - - - - - wq13ea-10 wq13ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 178h: wq13ea-8 wq13ea-7 wq13ea-6 wq13ea-5 wq13ea-4 wq13ea-3 wq13ea-2 wq13ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 13 end address [10-1] this register specifies the end address for the wan queue 13. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq14ea register description: wan queue 14 end address register address: 17ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 17bh: - - - - - - wq14ea-10 wq14ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 17ah: wq14ea-8 wq14ea-7 wq14ea-6 wq14ea-5 wq14ea-4 wq14ea-3 wq14ea-2 wq14ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 14 end address [10-1] this register specifies the end address for the wan queue 14. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 215 of 375 register name: ar.wq15ea register description: wan queue 15 end address register address: 17ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 17dh: - - - - - - wq15ea-10 wq15ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 17ch: wq15ea-8 wq15ea-7 wq15ea-6 wq15ea-5 wq15ea-4 wq15ea-3 wq15ea-2 wq15ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 15 end address [10-1] this register specifies the end address for the wan queue 15. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wq16ea register description: wan queue 16 end address register address: 17eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 17fh: - - - - - - wq16ea-10 wq16ea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 17eh: wq16ea-8 wq16ea-7 wq16ea-6 wq16ea-5 wq16ea-4 wq16ea-3 wq16ea-2 wq16ea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan queue 16 end address [10-1] this register specifies the end address for the wan queue 16. the value specifies the most significant 10 bits of the s dram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 216 of 375 register name: ar.liqsa register description: lan insert queue start address register address: 180h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 181h: - - - - - liqpr liqsa-10 liqsa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 180h: liqsa-8 liqsa-7 liqsa-6 liqsa-5 liqsa-4 liqsa-3 liqsa-2 liqsa-1 default 0 0 0 0 0 0 0 0 bit 10: lan insert queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan insert queue start address [10-1] this register specifies the st art address for the lan insert queue. the value specifies the most significant 10 bits of the sdram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.liqea register description: lan insert queue end address register address: 182h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 183h: - - - - - - liqea-10 liqea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 182h: liqea-8 liqea-7 liqea-6 liqea-5 liqea-4 liqea-3 liqea-2 liqea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan insert queue end address [10-1] this register specifies the e nd address for the lan insert queue. the value specifies the most significant 10 bits of the sdram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 217 of 375 register name: ar.leqsa register description: lan extract queue start address register address: 184h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 185h: - - - - - leqpr leqsa-10 leqsa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 184h: leqsa-8 leqsa-7 leqsa-6 leqsa-5 leqsa-4 leqsa-3 leqsa-2 leqsa-1 default 0 0 0 0 0 0 0 0 bit 10: lan extract queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: lan extract queue start address [10-1] this register specifies the st art address for the lan extract queue. the value specifies the most significant 10 bits of the sdram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.leqea register description: lan extract queue end address register address: 186h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 187h: - - - - - - leqea-10 leqea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 186h: leqea-8 leqea-7 leqea-6 leqea-5 leqea-4 leqea-3 leqea-2 leqea-1 default 0 0 0 0 0 0 0 0 bits 0-9: lan extract queue end address [10-1]. this register specifies the e nd address for the lan extract queue. the value specifies the most significant 10 bits of the sdram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 218 of 375 register name: ar.wiqsa register description: wan insert queue start address register address: 188h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 189h: - - - - - wiqpr wiqsa-10 wiqsa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 188h: wiqsa-8 wiqsa-7 wiqsa-6 wiqsa-5 wiqsa-4 wiqsa-3 wiqsa-2 wiqsa-1 default 0 0 0 0 0 0 0 0 bit 10: wan insert queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 0-9: wan insert queue start address [10-1] this register specifies the st art address for the wan insert queue. the value specifies the most significant 10 bits of the sdram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.wiqea register description: wan insert queue end address register address: 18ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 18bh: - - - - - - wiqea-10 wiqea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 18ah: wiqea-8 wiqea-7 wiqea-6 wiqea-5 wiqea-4 wiqea-3 wiqea-2 wiqea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan insert queue end address [10-1] this register specifies the e nd address for the wan insert queue. the value specifies the most significant 10 bits of the sdram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 219 of 375 register name: ar.weqsa register description: wan extract queue start address register address: 18ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 18dh: - - - - - weqpr weqsa-10 weqsa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 18ch: weqsa-8 weqsa-7 weqsa-6 weqsa-5 weqsa-4 weqsa-3 weqsa-2 weqsa-1 default 0 0 0 0 0 0 0 0 bit 10: wan extract queue pointer reset. 0 = no reset of the queue pointers (the user may be re-configuring to the same value) 1 = momentary reset of queue pointers (user is not required to change value to ?0? to conclude reset) bits 9-0: wan extract queue start address [10-1] this register specifies the st art address for the wan extract queue. the value specifies the most significant 10 bits of the sdram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.weqea register description: wan extract queue end address register address: 18eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 18fh: - - - - - - weqea-10 weqea-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 18eh: weqea-8 weqea-7 weqea-6 weqea-5 weqea-4 weqea-3 weqea-2 weqea-1 default 0 0 0 0 0 0 0 0 bits 0-9: wan extract queue end address [10-1] this register specifies the e nd address for the wan extract queue. the value specifies the most significant 10 bits of the sdram absolute address, resulting in a granularity of 32,768 bytes per lsb.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 220 of 375 register name: ar.lqw register description: lan queue watermark register address: 190h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 191h: - - - lqw-13 lqw-12 lqw-11 lqw-10 lqw-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 190h: lqw-8 lqw-7 lqw-6 lqw-5 lqw-4 lqw-3 lqw-2 lqw-1 default 0 0 0 0 0 0 0 0 bits 0-12: lan queue watermark [lqw 13-1] this register specifies the wate rmark threshold that is used to trigger a lan pause control frame. one value is used for all 16 queues (each queue is independently enabled and tested). the value from this register is multiplied by 64 to determine the minimum number of bytes available in each ddr sdram lan queue after flow contro l (or lan queue watermark interrupt) is triggered. the maximum valid value is decimal 8191, which designates that a mini mum of 8191 x 64 bytes = 524,224 bytes can be stored after the watermark is reached. the lowest valid setting is dec imal 3, or a minimum of 192 bytes available when flow control is triggered. the purpose of the lqw setting is to prevent data loss due to queue overflow. the lqw setting is independent of the cir policing function that monitors the rate at which data is received irrespective of the fill level of the queue. for applications with maximum packet length < 2049 and wi th a short ethernet phy transmission distance (< 25 meters) it is recommended that the lqw be set to a minimum value of 57. for applications that include a long ethernet phy tran smission distance the lqw setting can be increased. for gbe applications the lqw value can be increased by 1 for each additional 88 meters (up to lqw = 8191 or 715km). for 100mbps each incremental step will support 880 meters (at 100mbps there is less/slower data on the transmission line). for 10mbps each incremental step w ill support 8,800 meters. it is recommended that the user verify the lqw setting in long ethernet transmission line applications.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 221 of 375 register name: ar.mqc register description: miscellaneous queue control register address: 192h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 193h: - - - - - - fpepd wqode default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 192h: wirrw2 wirrw1 wienc2 wienc1 wispl wiena wqpd asqpr default 0 0 0 0 0 0 0 0 bit 9: fractional packet error purge disable (fpepd) 0 = fractional frame error purge enabled. 1 = fractional frame error purge disabled. bit 8: wan queue overflow discard enable (wqode) setting used for all 16 wan queues. 0 = overflow discard enabled. 1 = overflow discard disabled. this setting is used for all 16 wan queues. when wqode = 0 and an overflow condition occurs on a wan queue, that entire queue is discarded. this bit setti ng is independent of the preemptive discard (wqpd). bits 6-7: wan insert round robin weight (wirrw[2:1]) 00: round robin weight = 1. 01: round robin weight = 2. 10: round robin weight = 4. 11: round robin weight = 8. only valid in forwarding mode 2, when lqsm = 1 (weighted round robin scheduling). bits 4-5: wan insert encapsulator (wienc[2:1]) 00 = multiplexed with data from encapsulator #1 (wan group1). 01 = multiplexed with data from encapsulator #2 (wan group 2). 10 = multiplexed with data from encapsulator #3 (wan group 3). 11 = multiplexed with data from encapsulator #4 (wan group 4). bit 3: wan insert strict priority level (wispl]) for lqsm = 0 (strict priority scheduling; the lqsm bit is defined in the lqsc register below) 0: wan insert using priority level 1.5; inse rted frames scheduled ahead of levels 2, 3, 4. 1: wan insert using priority level 3.5; inserted frames scheduled ahead of level 4. note: only valid when using strict priority scheduling (lqsm = 0). bit 2: wan insert enable (wiena). 0 = wan insertion is disabled. 1 = wan insertion is enabled. bit 1: wan queue preemptive discard (wqpd). 0 = disabled. 1 = enabled. frames are discarded when the wan queue high threshold is exceeded. bit 0: all sdram queue pointer reset. (asqpr) 0 = normal operation. 1 = momentary reset of all wan, lan, insert and extract queue pointers.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 222 of 375 register name: ar.lqsc register description: lan queue scheduling control register address: 194h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 195h: - - - - - - - lqsm default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 194h: lq4rrw-2 lq4rrw-1 lq3rrw-2 lq3rrw -1 lq2rrw-2 lq2rrw-1 lq1rrw-2 lq1rrw-1 default 0 0 0 0 0 0 0 0 bit 8: lan queue scheduling mode (lqsm) 0 = strict priority scheduling between lan queues wi thin the same lan queue group (enabled for all 4 lan queue groups) and the wan insert channel 1 = weighted round robin (wrr) scheduling between lan queues within lan queue group #1 and with the wan insert channel. when lqsm = 1, the other 3 lan queue groups (12 lan queues) are not allowed. wrr scheduling mode is only available in forwarding mode 2, with a single lan port enabled. bit 6-7: lan queue 4 round robin weighting (lq4rrw [2:1]) 00: round robin weight = 1 01: round robin weight = 2 10: round robin weight = 4 11: round robin weight = 8 bit 4-5: lan queue 3 round robin weighting (lq3rrw [2:1]) 00: round robin weight = 1 01: round robin weight = 2 10: round robin weight = 4 11: round robin weight = 8 bit 2-3: lan queue 2 round robin weighting (lq2rrw [2:1]) 00: round robin weight = 1 01: round robin weight = 2 10: round robin weight = 4 11: round robin weight = 8 bit 0-1: lan queue 1 round robin weighting (lq1rrw [2:1]) 00: round robin weight = 1 01: round robin weight = 2 10: round robin weight = 4 11: round robin weight = 8
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 223 of 375 register name: ar.bftoa register description: bridge filter table offset address register address: 196h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 197h: - - - - - - bftoa-10 bftoa-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 196h: bftoa-8 bftoa-7 bftoa-6 bftoa-5 bftoa-4 bftoa-3 bftoa-2 bftoa-1 default 0 0 0 0 0 0 0 0 bits 0-9: bridge filter tabl e offset address (bftoa[10-1]) this register specifies t he offset address for the bridge table. the value specifies the most significant 10 bits of the sdram absolute address, resulting in a granularity of 32,768 bytes per lsb. register name: ar.lqos register description: lan queue overflow status register address: 198h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 199h: lqos-16 lqos-15 lqos-14 lqos-13 lqos-12 lqos-11 lqos-10 lqos-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 198h: lqos-8 lqos-7 lqos-6 lqos-5 lqos-4 lqos -3 lqos-2 lqos-1 default 0 0 0 0 0 0 0 0 bits 0-15: lan queue overflow status (lqos[16-1]) this register indicates whether an overflow condition has occurred on any of the lan queues since the last read of this register (one status bit per lan queue). this register is reset each time it is read. 0 = no overflow condition detected 1 = at least one overflow condition detected since last read
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 224 of 375 register name: ar.lqoim register description: lan queue overflow interrupt mask register address: 19ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 19bh: lqoim-16 lqoim-15 lqoim-14 lqoim-13 lqoim-12 lqoim-11 lqoim-10 lqoim-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 19ah: lqoim-8 lqoim-7 lqoim-6 lqoim-5 lqoim-4 lqoi m-3 lqoim-2 lqoim-1 default 0 0 0 0 0 0 0 0 bits 0-15: lan queue overflow interrupt mask (lqoim[16-1]) this register provides an interrupt bit mask to filter out unwanted interrupts. 0 = bit mask disabled 1 = bit mask enabled register name: ar.lqnfs register description: lan queue near full status register address: 19ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 19dh: lqnfs-16 lqnfs-15 lqnfs- 14 lqnfs-13 lqnfs-12 lqnf s-11 lqnfs-10 lqnfs-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 19ch: lqnfs-8 lqnfs-7 lqnfs- 6 lqnfs-5 lqnfs-4 lqnf s-3 lqnfs-2 lqnfs-1 default 0 0 0 0 0 0 0 0 bits 0-15: lan queue near full status (lqnfs[16-1]) this register indicates whether any of the lan queues have exceeded the lan queue watermark defined in ar.lqw since the last read of this register (one status bit per lan queue). this register is reset each time it is read. 0 = no near full condition detected 1 = at least one near full condition detected since last read
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 225 of 375 register name: ar.lqnfim register description: lan queue near full interrupt mask register address: 19eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 19fh: lqnfim-16 lqnfim-15 lqnfim-14 lqnfim-13 lqnfim-12 lqnfim-11 lqnfim-10 lqnfim-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 19eh: lqnfim-8 lqnfim-7 lqnfim-6 lqnfim-5 lqnfim-4 lqnf im-3 lqnfim-2 lqnfim-1 default 0 0 0 0 0 0 0 0 bits 0-15: lan queue near full interrupt mask (lqnfim[16-1]) this register provides an interrupt bit mask to filter out unwanted interrupts. 0 = bit mask disabled 1 = bit mask enabled register name: ar.wqos register description: wan queue overflow status register address: 1a0h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1a1h: wqos-16 wqos-15 wqos-14 wqos-13 wqos-12 wqos-11 wqos-10 wqos-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1a0h: wqos-8 wqos-7 wqos-6 wqos-5 wqos-4 wqos-3 wqos-2 wqos-1 default 0 0 0 0 0 0 0 0 bits 0-15: wan queue overflow status (wqos[16-1]) this register indicates whether an overflow condition has occurred on any of the wan queues since the last read of this register (one status bit per wan queue). this register is reset each time it is read. 0 = no overflow condition detected 1 = at least one overflow condition detected since last read
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 226 of 375 register name: ar.wqoim register description: wan queue overflow interrupt mask register address: 1a2h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1a3h: wqoim-16 wqoim-15 wqoim-14 wqoim-13 wqoim-12 wqoim-11 wqoim-10 wqoim-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1a2h: wqoim-8 wqoim-7 wqoim-6 wqoim-5 wqoim-4 wqoim-3 wqoim-2 wqoim-1 default 0 0 0 0 0 0 0 0 bits 0-15: wan queue overflow interrupt mask (wqoim[16-1]) this register provides an interrupt bit mask to filter out unwanted interrupts. 0 = bit mask disabled 1 = bit mask enabled register name: ar.wqnfs register description: wan queue near full status register address: 1a4h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1a5h: wqnfs-16 wqnfs-15 wqnfs-14 wqnfs-13 wqnfs-12 wqnfs-11 wqnfs-10 wqnfs-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1a4h: wqnfs-8 wqnfs-7 wqnfs-6 wqnfs-5 wqnfs-4 wqnfs-3 wqnfs-2 wqnfs-1 default 0 0 0 0 0 0 0 0 bits 0-15: wan queue near full status (wqnfs[16-1]) this register indicates whether an impending overflow condition has occurred on a wan queue, and the device initiated the discarding of incoming frames on a wan interface. this condition can occur if the transmit lan interface is disabl ed, if the mac has received excessive pause flow control frames and completely filled the bu ffers for the transmit lan while responding to the pause requests, or if operating in half duplex mode with heavy lan network congestion. this register is cleared each time it is read. 0 = normal operation 1 = at least one ?near full? condition detected since last read, frames may have been discarded.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 227 of 375 register name: ar.wqnfim register description: wan queue near full interrupt mask register address: 1a6h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1a7h: wqnfim-16 wqnfim-15 wqnfim-14 wqnfim-1 3 wqnfim-12 wqnfim-11 wqnfim-10 wqnfim-9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1a6h: wqnfim-8 wqnfim-7 wqnfim-6 wqnfim-5 wqnfim-4 wqnfim-3 wqnfim-2 wqnfim-1 default 0 0 0 0 0 0 0 0 bits 0-15: wan queue near full interrupt mask (wqnfim[16-1]) this register provides an interrupt bit mask to filter interrupts based on the status conditions in the ar.wqnfs register. 0 = bit mask disabled 1 = bit mask enabled register name: ar.eqos register description: extract queue overflow status register address: 1a8h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1a9h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1a8h: - - - - - - weqos leqos default 0 0 0 0 0 0 0 0 bit 1: wan extract queue overflow status [weqos] this bit indicates whether an overflow condition has occurred on the lan extract queue since the last read of this register. this register is reset each time it is read. 0 = no overflow condition detected 1 = at least one overflow condition detected since last read bit 0: lan extract queue overflow status [leqos] this bit indicates whether an overflow condition has occurred on the lan extract queue since the last read of this register. this register is reset each time it is read. 0 = no overflow condition detected 1 = at least one overflow condition detected since last read
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 228 of 375 register name: ar.eqoim register description: extract queue overflow interrupt mask register address: 1aah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1abh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1aah: - - - - - - weqoim leqoim default 0 0 0 0 0 0 0 0 bit 1: wan extract queue overflow interrupt mask [weqoim] this bit provides an interrupt bit mask to filter out unwanted interrupts. 0 = bit mask disabled 1 = bit mask enabled bit 0: lan extract queue overflow interrupt mask [leqoim] this bit provides an interr upt bit mask to filter out unwanted interrupts. 0 = bit mask disabled 1 = bit mask enabled
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 229 of 375 register name: ar.bmis register description: buffer manager(arbiter) interrupt status register address: 1ach bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1adh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1ach: - - - eqoi wqnfi wqoi lcnfi lqoi default 0 0 0 0 0 0 0 0 bit 4: extract queue overflow interrupt [eqoi] this bit provides an indication of whether this is an active interrupt. this bit should not be latched, but should provi de a logical or of the extract queue overflow status register bits (any ?1? generates an interrupt). 0 = no active interrupt 1 = active interrupt bit 3: wan queue near full interrupt [wqnfi] this bit provides an indication of whether this is an active interrupt. this bit should not be latched, but should prov ide a logical or of the wan queue near full status register bits (any ?1? generates an interrupt). 0 = no active interrupt 1 = active interrupt bit 2: wan queue overflow interrupt [wqoi] this bit provides an indication of whether this is an active interrupt. this bit should not be latched, but should prov ide a logical or of the wan queue overflow status register bits (any ?1? generates an interrupt). 0 = no active interrupt 1 = active interrupt bit 1: lan queue near full interrupt [lqnfi] this bit provides an indication of whether this is an active interrupt. this bit should not be latched, but should prov ide a logical or of the lan queue near full status register bits (any ?1? generates an interrupt). 0 = no active interrupt 1 = active interrupt bit 0: lan queue overflow interrupt [lqoi] this bit provides an indication of whether this is an active interrupt. this bit should not be latched, but should provide a logical or of the lan queue overflow status register bits (any ?1? generates an interrupt). 0 = no active interrupt 1 = active interrupt
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 230 of 375 10.5 packet processor (encapsulator) registers note that some devices in the product family have less than four encapsulators. the ds33x11 contains only encapsulator #1. the ds33w41 and ds33x42 devic es contain only encapsulators #1 and #3. register name: pp.emcr register description: encapsulator master control register register address: 200h (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 201h: egcm eprtsel efcsad ecfcrd efcs16en - efcsb ebbys default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 200h: eiis elhde et1e et2e ere1 ere0 tbre ehcbo default 0 0 0 0 0 0 0 0 bit 15: encapsulator gfp crc mode(egcm) 0= gfp null. encapsulator pfcs calculation begins with the 9 th byte after the start of the frame. 1= gfp linear. encapsulator pfcs calculation begins with the 13 th byte after the start of the frame. bit 14: encapsulator protocol selection (eprtsel) 0= gfp 1= hdlc/chd lc/laps(x.86) bit 13: encapsulator frame check sequence append disable (efcsad) when set to 1, frames will not have a hdlc/gfp fcs appended prior to transmission. when equal to 0, the encapsulation fcs will be appended. bit 12: encapsulator scrambler disable (ecfcrd) when set to 1, encapsulation x 43 +1 scrambling is disabled. bit 11: encapsulator 16-bit fcs enable (efcs16en) ? when set to 1, the hdlc encapsulation uses a 16-bit fcs. when equal to 0, a 32 bit fcs is appended. this bit only applies when efcsad = 0. bit 9: encapsulator ethernet fcs bypass (efcsb) when set to 1, the ethernet fcs is forwarded exactly as received. when equal to 0, the ethernet fcs is removed prior to encapsulation. bit 8: encapsulator bit byte synchronous (ebbys) when set to 1, the encapsulator performs byte stuffing. when equal to 0, the encapsulator performs bit stuffing. when in gfp mode ( eprtsel = 0 ), this bit should be set to 1. bit-stuffed hdlc is no t valid for multi-member vcgs. bit 7: encapsulator inte rframe idle selection (eiis) when set to 1, the encapsulator idle sequence is 0xff. when equal to 0, the encapsulator idle sequence is 0x7e. this bit only applies when eprtsel = 1 . bit 6: encapsulator line header enable (elhde) when set to 1, the encapsulat or will insert the values in pp.elhhr and pp.elhlr as a 4-byte line header. the header is appended after the pli+chec field in gfp mode, and after the start flag in hdlc mode. bit 5: encapsulator tag 1 enable (et1e) when set to 1, the encapsulator will insert the values in pp.et1dhr and pp.et1dlr as a 4-byte tag immediately before the da field. bit 4: encapsulator tag 2 enable (et2e) when set to 1, the encapsulator will insert the values in pp.et2dhr and pp.et2dlr as a 4-byte tag immediately after the sa field. bits 2-3: encapsulator remove enable (ere[1:0]) 00 = normal operation. 01 = 18 bytes are removed from the frame prior to encapsulation, starting with the da field. 10 = 14 bytes are removed from the frame prior to encapsulation, starting with the da field. 11 = reserved. bit 1: transmit bit reorder (tbre) controls the endian order of hdlc transmission. this bit function is not available in device revision a1 ( gl.idr.revn=000).
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 231 of 375 0 = hdlc payload will be transmitted msb-first. default operation. 1 = hdlc payload will be transmitted lsb-first. bit 0: encapsulator hdlc crc bit reorder (ehcbo) controls the endian order of the hdlc crc calculation. this bit function is not available in device revision a1 ( gl.idr.revn=000). 0 = hdlc crc will be calculated msb-first. default operation. 1 = hdlc crc will be calculated lsb-first. register name: pp.elhhr register description: encapsulator line header high data register register address: 202h (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 203h: elhd31 elhd30 elhd29 elhd28 elhd27 elhd26 elhd25 elhd24 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 202h: elhd23 elhd22 elhd21 elhd20 elhd19 elhd18 elhd17 elhd16 default 0 0 0 0 0 0 0 0 bits 0-15: encapsulator line header data (elhd[31:16]) these 2 bytes provide the mo st significant bytes of the line header, when enabled with elhde. eldh[31:25] is inserted first, followed by elhd[23:16]. register name: pp.elhlr register description: encapsulator line header low data register register address: 204h (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 205h: elhd15 elhd14 elhd13 elhd12 elhd11 elhd10 elhd9 elhd8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 204h: elhd7 elhd6 elhd 5 elhd4 elhd3 elhd2 elhd1 elhd0 default 0 0 0 0 0 0 0 0 bits 0-15: encapsulator line header data (elhd[15:0]) these 2 bytes provide the least significant bytes of the line header, when enabled with elhde. eldh[15: 8] is inserted first, followed by elhd[7:0].
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 232 of 375 register name: pp.et1dhr register description: encapsulator tag 1 data high register register address: 206h (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 207h: et1d31 et1d30 et1d29 et1d28 et1d27 et1d26 et1d25 et1d24 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 206h: et1d23 et1d22 et1d21 et1d20 et1d19 et1d18 et1d17 et1d16 default 0 0 0 0 0 0 0 0 bits 0-15: encapsulator tag 1 data (et1d[31:16]) these 2 bytes provide the most significant bytes of tag 1, when enabled with et1e. et1d[31:25] is inserted first, followed by et1d[23:16]. register name: pp.et1dlr register description: encapsulator tag 1 data low register register address: 208h (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 209h: et1d15 et1d14 et1d13 et1d12 et1d11 et1d10 et1d9 et1d8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 208h: et1d7 et1d6 et1d5 et1d4 et1d3 et1d2 et1d1 et1d0 default 0 0 0 0 0 0 0 0 bits 0-15: encapsulator tag 1 data (et1d[15:0]) these 2 bytes provide the least significant bytes of tag 1, when enabled with et1e. et1d[15:8] is inserted first, followed by et1d[7:0]. register name: pp.et2dhr register description: encapsulator tag 2 data high register register address: 20ah (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 20bh: et2d31 et2d30 et2d29 et2d28 et2d27 et2d26 et2d25 et2d24 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 20ah: et2d23 et2d22 et2d21 et2d20 et2d19 et2d18 et2d17 et2d16 default 0 0 0 0 0 0 0 0 bits 0-15: encapsulator tag 2 data (et2d[31:16]) these 2 bytes provide the most significant bytes of tag 2, when enabled with et2e. et2d[31:25] is inserted first, followed by et2d[23:16].
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 233 of 375 register name: pp.et2dlr register description: encapsulator tag 2 data low register register address: 20ch (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 20dh: et2d15 et2d14 et2d13 et2d12 et2d11 et2d10 et2d9 et2d8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 20ch: et2d7 et2d6 et2d5 et2d4 et2d3 et2d2 et2d1 et2d0 default 0 0 0 0 0 0 0 0 bits 0-15: encapsulator tag 2 data (et2d[15:0]) these 2 bytes provide the least significant bytes of tag 2, when enabled with et2e. et2d[15:8] is inserted first, followed by et2d[7:0]. register name: pp.eeir register description: encapsulator error insertion register register address: 20eh (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 20fh: eplieie edeie eefcseie efcf eie ebdec1 ebdec0 eei7 eei6 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 20eh: eei5 eei4 eei3 eei2 eei1 eei0 esei - default 0 0 0 0 0 0 0 0 bit 15: encapsulator pli error insert enable (eplieie) when set to 1, a single-bit error insertion is enabled for the pli field. this includes the 2 pli header bits and the corresponding chec. bit 14: encapsulator data error insert enable (edeie) when set to 1, a single-bit error insertion is enabled for the data field. errors can only be inserted in the first by te of the payload data. hence the ebd bit setting has no effect for inserting payload errors. bit 13: encapsulator ethernet fcs error insert enable (efcseie) when set to 1, a single-bit error insertion is enabled for the ethernet fcs field. bit 12: encapsulator fcs error insert enable (eplieie) when set to 1, a single-bit error insertion is enabled for the encapsulation fcs field. bits 10-11: encapsulator byte decode (ebd[1:0]) these bits determine which of the 4 bytes need error insertion for the pli, ethernet fcs, and encapsulation fcs fields . these bits have no effect on data error insertion. bits 2-9: encapsulator error insert (eie[7:0]) these 8 bits determine the bit location of the error insertion in the selected field. only one error is inserted for each tr ansition of esei. bit 1: encapsulator si ngle error insert (esei) changing this bit from a 0 to a 1 causes a single error insertion. for a second error insertion, the user must first clear this bit. register name: pp.efclsr register description: encapsulator frame count latched status register register address: 210h (+ 040h x (n-1), wan group encapsulator n=1 to 4)
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 234 of 375 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 211h: efcnt15 efcnt14 efcnt13 efcnt12 efcnt11 efcnt10 efcnt9 efcnt8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 210h: efcnt7 efcnt6 efcnt5 efcnt4 efcnt3 efcnt2 efcnt1 efcnt0 default 0 0 0 0 0 0 0 0 bits 0-15: encapsulator fr ame count (efcnt[15:0]) this counter provides the number of frames that have been encapsulated. the counter is reset upon being read by the microprocessor. register name: pp.esmls register description: encapsulator state machine latched status register address: 21eh (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 21fh: - - - - sople sopse cople copse default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 21eh: eople eopse - fuf fovf flok ff fe default 0 0 0 0 0 0 0 0 bit 11: (sople) this bit is set upon detection of an internal error. bit 10: (sopse) this bit is set upon detection of an internal error. bit 9: (cople) this bit is set upon detection of an internal error. bit 8: (copse) this bit is set upon detection of an internal error. bit 7: (eople) this bit is set upon detection of an internal error. bit 6: (eopse) this bit is set upon detection of an internal error. bit 4: (fuf) this bit is set if t he encapsulator fifo has underflowed. bit 3: (fovf) this bit is set if the encapsulator fifo has overflowed. bit 2: (flok) this bit is set if the encapsulator fifo is ok to accept more data. cleared on read. bit 1: (ff) this bit is set if the enca psulator fifo is full. cleared on read. bit 0: (fe) this bit is set if the enca psulator fifo is empty. cleared on read.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 235 of 375 register name: pp.esmie register description: encapsulator state machine interrupt enable register address: 220h (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 221h: - - - - sopleie sopseie copleie copseie default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 220h: eopleie eopseie - fufie fovfie flokie ffie feie default 0 0 0 0 0 0 0 0 bit 11: (sopleie) this bit enables an interrupt on the sople condition. bit 10: (sopseie) this bit enables an interrupt on the sopse condition. bit 9: (copleie) this bit enables an interrupt on the cople condition. bit 8: (copseie) this bit enables an interrupt on the copse condition. bit 7: (eopleie) this bit enables an interrupt on the eople condition. bit 6: (eopseie) this bit enables an interrupt on the eopse condition. bit 4: (fufie) this bit enables an interrupt on the fuf condition. bit 3: (fovfie) this bit enables an interrupt on the fovf condition. bit 2: (flokie) this bit enables an interrupt on the flok condition. bit 1: (ffie) this bit enables an interrupt on the ff condition. bit 0: (feie) this bit enables an interrupt on the fe condition. register name: pp.ehfl register description: encapsulator hdlc fill length register address: 226h (+ 040h x (n-1), wan group encapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 227h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 226h: ehfl7 ehfl6 ehfl5 ehfl4 ehfl3 ehfl2 ehfl1 ehfl0 default 0 0 0 0 0 0 0 0 bits 0-15: encapsulator hdlc fill length (ehfl[7:0]) used to set the minimum number of hdlc fill flags to be inserted after the end of each frame. only valid when hdlc encapsulation is used.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 236 of 375 10.6 decapsulator registers register name: pp.dmcr register description: decapsulator master control register register address: 300h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 301h: dgcm dprtsel dfcsad dcf crd dfcs16en - dbbs rbre default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 300h: dr1e dr2e dr3e dae1 dae0 dgsc dhrae dhcbo default 0 0 0 0 0 0 0 0 bit 15: decapsulator gfp crc mode (dgcm) 0=gfp null. decapsulator does not verify the ehec value. 1=gfp linear. decapsulator verifies the ehec value and discards failing frames. bit 14: decapsulator protocol selection (dprtsel) selects between gfp and hdlc based forms of encapsu lation. additionally, when transitioning hdlc between byte and bit modes of operation, this byte is used to rese t the hdlc circuitry. in order to initiate a reset the hdlc circuitry during bit/byte stuffing mode changes, this bi t must be set to zero briefly, then set back to 1. 0=gfp based. 1=hdlc based. bit 13: decapsulator frame check sequence append disable (dfcsad) ? when equal to 0, the incoming frame?s encapsulation (hdlc/gfp) c rc (fcs) will be validated and remove d. when set to 1, the decapsulated frame will not be expected to contain an encapsu lation crc and no bytes will be removed. bit 12: decapsulator scrambler disable (dcfcrd) when set to 1, the x 43 +1 descrambler is turned off. bit 11: decapsulator 16-bit fcs enable (dfcs16en) when set to 1 the decapsulated frame must contain a 16- bit fcs. when equal to zero, a 32-bit fcs is expected. this bit is relevant if dfcsad is reset. bit 9: decapsulator bit byte synchronous(dbbs) when set to 1, the decapsulator expects byte-stuffed hdlc. when equal to zero, the decapsulator expects bit-st uffed hdlc. when in gfp mode (dprtsel = 0), this bit should be set to 1. after changing this bit, the hdlc circuitry should be reset using the pp.dmcr.dprtsel bit. bit-stuffed hdlc is not valid fo r multi-member vcgs (wan groups). bit 8: receive bit reorder (rbre) controls the endian order of hdlc reception. this bit function is not available in device revision a1 ( gl.idr.revn=000). 0 = hdlc payload will be received msb-first. default operation. 1 = hdlc payload will be received lsb-first. bit 7: decapsulator remove function 1 enable (dr1e) when set to 1, 4 bytes are removed immediately after the chec bytes (for gfp) or start of hdlc flag (for hd lc). this bit should be set to 1 for x.86, cisco hdlc and gfp transport. this bit should be reset to 0 for hdlc traffic with no headers. bit 6: decapsulator remove function 2 enable (dr2e) when set to 1, 4 bytes are removed after the first remove function. this function should always be used in conjunction with decapsulator remove function 1. bit 5: decapsulator remove function 3 enable (dr3e) when set to 1, 12 bytes are skipped and then 4 bytes are removed. the 12 bytes are skipped after either decaps ulator remove function 1 and/or decapsulator remove function 2 have been performed (when enabled). when deca psulator remove functions 1 and 2 are disabled, 12 bytes are skipped from the beginning of the frame.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 237 of 375 bits 3-4: decapsulator add enable (dae[1:0]) controls the insertion of additional bytes by the decapsulator. 00 = normal operation. 01 = the 18 byte value from the pp.da1dr through pp.da9dr registers will be inserted after the chec bytes in gfp mode, or after the hdlc header/flag when in hdlc mode. 10 = the 14 byte value from the pp.da1dr through pp.da7dr registers will be inserted after the chec bytes in gfp mode, or after the hdlc header/flag when in hdlc mode. 11 = reserved. bit 2: decapsulator gfp synchronization control (dgsc) when set, ?triple synchronization? is selected. three consecutive plis and respective chec must be correct to enter the synchronization state. if equal to zero, two consecutive correct plis and checs are required. only applicable to gfp mode. bit 1: decapsulator hdlc rate adaptation (dhrae) 0= disabled. default for non-x.86 (laps) modes. 1= enabled. ?7d dd? sequence removed from data stream. for use in x.86 (laps) mode. bit 0: decapsulator hdlc crc bit order (dhcbo) controls the endian order of the hdlc crc calculation. this bit function is not available in device revision a1 ( gl.idr.revn=000). 0 = hdlc crc will be calculated msb-first. default operation. 1 = hdlc crc will be calculated lsb-first. register name: pp.da1dr register description: decapsulator add 1 data register register address: 302h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 303h d1d15d d1d14d d1d13d d1d12d d1d11d d1d10d d1d9d d1d8d default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 302h d1d7d d1d6d d1d5d d1d4d d1d3d d1d2d d1d1d d1d0d default 0 0 0 0 0 0 0 0 bits 0-15: decapsulator 1 data high (d1d [15:0]) these 2 bytes provide the data if the addition is enabled with pp.dmcr.dae[1:0]. register name: pp.da2dr register description: decapsulator add 2 data register register address: 304h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 305h: d2d15d d2d14d d2d13d d2d12d d2d11d d2d10d d2d9d d2d8d default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 304h: d2d7d d2d6d d2d5d d2d4d d2d3d d2d2d d2d1d d2d0d default 0 0 0 0 0 0 0 0 bits 0-15: decapsulator 2 data (d2d [15:0]) these 2 bytes provide the data if the addition is enabled with pp.dmcr.dae[1:0].
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 238 of 375 register name: pp.da3dr register description: decapsulator add 3 data register register address: 306h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 307h: d3d15d d3d14d d3d13d d3d12d d3d11d d3d10d d3d9d d3d8d default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 306h: d3d7d d3d6d d3d5d d3d4d d3d3d d3d2d d3d1d d3d0d default 0 0 0 0 0 0 0 0 bits 0-15: decapsulator 3 data (d3d [15:0]) these 2 bytes provide the data if the addition is enabled with pp.dmcr.dae[1:0]. register name: pp.da4dr register description: decapsulator add 4 data register register address: 308h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 309h: d4d15d d4d14d d4d13d d4d12d d4d11d d4d10d d4d9d d4d8d default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 308h: d4d7d d4d6d d4d5d d4d4d d4d3d d4d2d d4d1d d4d0d default 0 0 0 0 0 0 0 0 bits 0-15: decapsulator 4 data (d4d [15:0]) these 2 bytes provide the data if the addition is enabled with pp.dmcr.dae[1:0]. register name: pp.da5dr register description: decapsulator add 5 data register register address: 30ah (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 30bh: d5d15d d5d14d d5d13d d5d12d d5d11d d5d10d d5d9d d5d8d default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 30ah: d5d7d d5d6d d5d5d d5d4d d5d3d d5d2d d5d1d d5d0d default 0 0 0 0 0 0 0 0 bits 0-15: decapsulator 5 data (d5d [15:0]) these 2 bytes provide the data if the addition is enabled with pp.dmcr.dae[1:0].
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 239 of 375 register name: pp.da6dr register description: decapsulator add 6 data register register address: 30ch (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 30dh: d6d15d d6d14d d6d13d d6d12d d6d11d d6d10d d6d9d d6d8d default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 30ch: d6d7d d6d6d d6d5d d6d4d d6d3d d6d2d d6d1d d6d0d default 0 0 0 0 0 0 0 0 bits 0-15: decapsulator 6 data (d6d [15:0]) these 2 bytes provide the data if the addition is enabled with pp.dmcr.dae[1:0]. register name: pp.da7dr register description: decapsulator add 7 data register register address: 30eh (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 30fh: d7d15d d7d14d d7d13d d7d12d d7d11d d7d10d d7d9d d7d8d default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 30eh: d7d7d d7d6d d7d5d d7d4d d7d3d d7d2d d7d1d d7d0d default 0 0 0 0 0 0 0 0 bits 0-15: decapsulator 7 data high (d7d [15:0]) these 2 bytes provide the dat a if the addition is enabled pp.dmcr.dae[1:0]. register name: pp.da8dr register description: decapsulator add 8 data register register address: 310h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 311h: d8d15d d8d14d d8d13d d8d12d d8d11d d8d10d d8d9d d8d8d default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 310h: d8d7d d8d6d d8d5d d8d4d d8d3d d8d2d d8d1d d8d0d default 0 0 0 0 0 0 0 0 bits 0-15: decapsulator 8 data (d8d [15:0]) these 2 bytes provide the data if the addition is enabled with pp.dmcr.dae[1:0].
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 240 of 375 register name: pp.da9dr register description: decapsulator add 9 data register register address: 312h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 313h: d9d15d d9d14d d9d13d d9d12d d9d11d d9d10d d9d9d d9d8d default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 312h: d9d7d d9d6d d9d5d d9d4d d9d3d d9d2d d9d1d d9d0d default 0 0 0 0 0 0 0 0 bits 0-15: decapsulator 9 data high (d9d [15:0]) these 2 bytes provide the data if the addition is enabled with pp.dmcr.dae[1:0]. register name: pp.dmlsr register description: decapsulator master latched status register register address: 314h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 315h: dgsls dgslls dglcls dglcsl s dffls - dchecfls dtchecfls default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 314h: dfur dfovf - - - - - - default 0 0 0 0 0 0 0 0 bit 15: decapsulator gfp sync latched status (dgsls) when set the gfp has achieved synchronization latched status. this bit is cleared upon a read. bit 14: decapsulator gfp sync loss latched status (dgslls) when set indicates that the gfp has lost synchronization. this bi t is cleared upon a read. bit 13: decapsulator gfp loss of client signal latched status (dglcls) when set indicates that the gfp loss of client signal management frame has a rrived. this bit is cleared upon a read. bit 12: decapsulator gfp loss of client synchronization latched status (dglcsls) when set indicates that the gfp loss of client synchronization management fram e has arrived. this bit is cleared upon a read. bit 11: decapsulator fcs fail latched status (dffls) when set indicates that the fcs has failed. this bit is cleared upon a read. bit 9: decapsulator extension header ehec fail latched status (dchecfls) when set indicates that the extension hec has failed. this bit is cleared upon a read. bit 8: decapsulator type hec fail latched status (dtchecfls) when set indicates type hec has failed. bit 7: decapsulator fifo under run latched status (dfur) when set indicates that the fifo has under run. bit 6: decapsulator fifo overflow latched status (dfovf) when set indicates that the fifo has overflowed.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 241 of 375 register name: pp.dmlsie register description: decapsulator master latched status interrupt enable register address: 316h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 317h: dgsie dgslie dglcie dglcsi e dffie - dchecfie dtchecfie default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 316h: dfurie dfovfie - - - - - - default 0 0 0 0 0 0 0 0 bit 15: decapsulator gfp sync interrupt enable (dgsie) bit 14: decapsulator gfp sync loss interrupt enable (dgslie) bit 13: decapsulator gfp loss of client signal interrupt enable (dglcie) bit 12: decapsulator gfp loss of client synchronization interrupt enable (dglcsie) bit 11: decapsulator fcs fail interrupt enable (dffie) bit 9: decapsulator extension header ehec fail interrupt enable (dchecfie) bit 8: decapsulator type hec fail interrupt enable (dtchecfie) bit 7: decapsulator fifo under run interrupt enable (dfurie) bit 6: decapsulator fifo overfl ow interrupt enable (dfovfie) register name: pp.dgplc register description: decapsulator good packet latched counter register address: 318h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 319h: dgplc15 dgplc14 dgplc13 dgplc12 dgplc11 dgplc10 dgplc9 dgplc8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 318h: dgplc7 dgplc6 dgplc5 dgplc4 dgplc3 dgplc2 dgplc1 dgplc0 default 0 0 0 0 0 0 0 0 bit 15-0/ decapsulator good packet low latched counter(dgplc 15:0) ? this bits provide the low word of the good frame counter. this counter is cleared upon a read.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 242 of 375 register name: pp.dgblc register description: decapsulator bad packet latched counter register address: 31ah (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 31bh: dbplc15 dbplc14 dbplc13 dbplc12 d bplc11 dbplc10 dbplc9 dbplc8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 31ah: dbplc7 dbplc6 dbplc5 dbplc4 dbplc3 dbpl c2 dbplc1 dbplc0 default 0 0 0 0 0 0 0 0 bit 8-15: decapsulator bad packet latched counter(dbplc 7:0) these bits provide the bad frame counter latched value. the counter is cleared upon a read. the following are counted: aborts, runt, fcs errors, type chec failures. register name: pp.dssr register description: decapsulator synchronization status register register address: 31ch (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 31dh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 31ch: - - - - - dgsync dgpsync dghunt default 0 0 0 0 0 0 0 0 bit 2: decapsulator gfp sync status (dgsync) this bit is set when gfp is sy nchronized. this bit can be read after the transition of dfsrwpc. bit 1: decapsulator gfp pre sync status (dgpsync) this bit is set when gfp synchronization machine is in the pre-synchronized state. this bit can be read after the transition of dfsrwpc . bit 0: decapsulator gfp hunt status (dhunt) this bit is set when gfp synchronization machine is in the hunt state. this bit can be read after the transition of dfsrwpc .
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 243 of 375 register name: pp.dhhsr register description: decapsulator header high status register register address: 31eh (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 31fh: dhsr31 dhsr30 dhsr29 dhsr28 dhsr27 dhsr26 dhsr25 dhsr24 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 31eh: dhsr23 dhsr22 dhsr21 dhsr20 dhsr19 dhsr18 dhsr17 dhsr16 default 0 0 0 0 0 0 0 0 bit 15-0: decapsulator header high status (dhsr31:16) ? these bits provide the high word of the header bytes that have been received. these are the first 2 bytes after the hdlc start flag and the first 2 bytes after the gfp pli and gfp chec. register name: pp.dhlsr register description: decapsulator header low status register register address: 320h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 321h: dhsr15 dhsr14 dhsr13 dhsr12 dhsr11 dhsr10 dhsr9 dhsr8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 320h: dhsr7 dhsr6 dhsr5 dhsr4 dhsr3 dhsr2 dhsr1 dhsr0 default 0 0 0 0 0 0 0 0 bit 15-0: decapsulator header low status (dhsr15:0) ? these bits provide the low word of the header bytes that have been received. these are t he bytes 3 and 4 after the hdlc start flag and bytes 3 and 4 after the gfp pli and gfp chec.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 244 of 375 register name: pp.dfscr register description: decapsulator fifo control register register address: 322h (+ 040h x (n-1), wan group decapsulator n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 323h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 322h: - - - - dem dsmre dfpre dfsrwpc default 0 0 0 0 0 0 0 0 note ? bit definitions below not symmetric decap/encap: bit 3: decapsulator error mode (dem) when set to 1, errored frames are forwarded. normally they are discarded. this bit function was located in dmcr bit 0 in device revision a1 ( gl.idr.revn=000). bit 2: decapsulator state machine reset (dsmre) if this bit is set and dfsrwpc transitions, the decapsulator state ma chine will be reset. bit 1: decapsulator fifo pointer reset enable (dfpre) - setting this bit to a 1 will enable the fifo to be reset. the fifo read and write pointer will be reset if dfsrwpc transitions and this bit is set. bit 0: decapsulator fifo and state r ead, write, and pmu control (dfsrwpc)- a 0 to 1 transition enables the fifo read and write addresses, status registers to be read by the proces sor. the user must wait 4 system clocks before the reads can be done. this bit is used to control resetting of the fifo read and write pointers and the decapsulator state machine. this bit is also used as a pmu update for all decapsulator latched counters.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 245 of 375 10.7 vcat/lcas registers 10.7.1 transmit vcat registers note: some registers are on a per-wan-port basis. register name: vcat.tcr1 register description: vcat transmit control register 1 register address: 400h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 401h: - - - - tgidbc tgidm tload tvblken default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 400h: v4fm1 v4fm0 v3fm1 v3fm0 v2fm1 v2fm0 v1fm1 v1fm0 default 0 0 0 0 0 0 0 0 bit 11: transmit gid bit convention (tgidbc) controls all 4 vcgs. this bit is only used when tgidm = 1 0 = bit 15 of the tgidx register is transmitted first. 1 = bit 0 of tgidx register is transmitted first. bit 10: transmit gid mode (tgidm) controls all 4 vcgs. 0 = prbs (2 15 ? 1) pattern. 1 = user configured value. the first bit inserted will be when mfi2 = xxxx_0000. bit 9: transmit configuration change load (tload). when all wan transmit ports have been configured with the correct sq assignments, ctrl commands, member count (tcr1.vnmc[3:0]), vcg assignments, and lcas enable (le[4:1]), a 0-to-1 transition on this bit will load the new configuration on the next vcat start of frame (sof). this register will update all vcgs. bit 8: transmit vcat block enable (tvblken) data path reset/disable. 0 = vcat block is disabled; data path is disabled 1 = vcat block is enabled; data path is enabled note: this bit must be set even in non-vcg modes bits 6-7: vcg4 frame mode control (v4fm[1:0]) 00 = vcg4 configured for t1 01 = vcg4 configured for e1 10 = vcg4 configured for c-bit ds3 (m ust be mapped to ports 1 to 8 only) 11 = vcg4 configured for e3 g.832 (mus t be mapped to ports 1 to 8 only) bits 4-5: vcg3 frame mode control (v3fm[1:0]) 00 = vcg3 configured for t1 01 = vcg3 configured for e1 10 = vcg3 configured for c-bit ds3 (m ust be mapped to ports 1 to 8 only) 11 = vcg3 configured for e3 g.832 (mus t be mapped to ports 1 to 8 only)
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 246 of 375 bits 2-3: vcg2 frame mode control (v2fm[1:0]) 00 = vcg2 configured for t1 01 = vcg2 configured for e1 10 = vcg2 configured for c-bit ds3 (m ust be mapped to ports 1 to 8 only) 11 = vcg2 configured for e3 g.832 (must be mapped to ports 1 to 8 only) bits 0-1: vcg1 frame mode control (v1fm[1:0]) 00 = vcg1 configured for t1 01 = vcg1 configured for e1 10 = vcg1 configured for c-bit ds3 (m ust be mapped to ports 1 to 8 only) 11 = vcg1 configured for e3 g.832 (mus t be mapped to ports 1 to 8 only)
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 247 of 375 register name: vcat.tcr2 register description: vcat transmit control register 2 register address: 402h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 403h: tv4mc3 tv4mc2 tv4mc1 tv4mc0 tv3mc3 tv3mc2 tv3mc1 tv3mc0 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 402h: tv2mc3 tv2mc2 tv2mc1 tv2mc0 tv1mc3 tv1mc2 tv1mc1 tv1mc0 default 0 0 0 0 0 0 0 0 bits 12-15: transmit vcg4 member count (tv4mc[3:0]) these bits indicate to the device the number of members assigned to vcg4 0000 = 1 member 0001 = 2 members 0010 = 3 members ?.. 1111 = 16 members bits 8-11: transmit vcg3 member count (tv3mc[3:0]) these bits indicate to the device the number of members assigned to vcg3 0000 = 1 member 0001 = 2 members 0010 = 3 members ?.. 1111 = 16 members bits 4-7: transmit vcg2 member count (tv2mc[3:0]) these bits indicate to the device the number of members assigned to vcg2 0000 = 1 member 0001 = 2 members 0010 = 3 members ?.. 1111 = 16 members bits 0-3: transmit vcg1 member count (tv1mc[3:0]) these bits indicate to the device the number of members assigned to vcg1 0000 = 1 member 0001 = 2 members 0010 = 3 members ?.. 1111 = 16 members note: if more than one member is assigned to a wan group, vcat must be enabled for that group. updates to this register take effect afte r vcgcr.tload transitions.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 248 of 375 register name: vcat.tlcr1 register description: vcat transmit lcas control register 1 register address: 406h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 407h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 406h: - - - - rsack4 rsack3 rsack2 rsack1 default 0 0 0 0 0 0 0 0 bits 0-3: vcgn resequence acknowledge (rsack[4:1]). 0 = no change 1 = invert rs-ack bit register name: vcat.tlcr2 register description: vcat transmit lcas control register 2 register address: 408h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 409h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 408h: - - - - atmstd4 atmstd3 atmstd2 atmstd1 default 0 0 0 0 0 0 0 0 bits 0-3: automatic transmit mst disable (atmstd[4:1]) 0 = rlcas automatic inserts transmit mst values for vcgn 1 = disable rlcas control of transmit mst for vcgn register name: vcat.tlcr3 register description: vcat transmit lcas control register 3 register address: 40ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 40bh: v1mst15 v1mst14 v1mst13 v1mst12 v1mst11 v1mst10 v1mst9 v1mst8 default 1 1 1 1 1 1 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40ah: v1mst7 v1mst6 v1mst5 v1mst4 v1mst3 v1mst2 v1mst1 v1mst0 default 1 1 1 1 1 1 1 1 bits 0-15: vcg 1 mst manual control (v1mst[15:0]) 0 = member n sends mst = ok 1 = member n sends mst = fail note: default upon power-up is set. these bits latched on sof if vcat.tlcr1.atmstd1 =1.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 249 of 375 register name: vcat.tlcr4 register description: vcat transmit lcas control register 4 register address: 40ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 40dh: v2mst15 v2mst14 v2mst13 v2mst12 v2mst11 v2mst10 v2mst9 v2mst8 default 1 1 1 1 1 1 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40ch: v2mst7 v2mst6 v2mst5 v2mst4 v2mst3 v2mst2 v2mst1 v2mst0 default 1 1 1 1 1 1 1 1 bits 0-15: vcg 2 mst manual control (v2mst[15:0]) 0 = member n sends mst = ok 1 = member n sends mst = fail note: default upon power-up is set. these bits latched on sof if vcat.tlcr1.atmstd2 =1. register name: vcat.tlcr5 register description: vcat transmit lcas control register 5 register address: 40eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 40fh: v3mst15 v3mst14 v3mst13 v3mst12 v3mst11 v3mst10 v3mst9 v3mst8 default 1 1 1 1 1 1 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40eh: v3mst7 v3mst6 v3mst5 v3mst4 v3mst3 v3mst2 v3mst1 v3mst0 default 1 1 1 1 1 1 1 1 bits 15 to 0: vcg 3 mst manual control (v3mst[15:0]) 0 = member n sends mst = ok 1 = member n sends mst = fail note: default upon power-up is set. these bits latched on sof if vcat.tlcr1.atmstd3 =1. register name: vcat.tlcr6 register description: vcat transmit lcas control register 6 register address: 410h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 411h: v4mst15 v4mst14 v4mst13 v4mst12 v4mst11 v4mst10 v4mst9 v4mst8 default 1 1 1 1 1 1 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 410h: v4mst7 v4mst6 v4mst5 v4mst4 v4mst3 v4mst2 v4mst1 v4mst0 default 1 1 1 1 1 1 1 1 bits 0-15: vcg 4 mst manual control (v4mst[15:0]) 0 = member n sends mst = ok 1 = member n sends mst = fail note: default upon power-up is set. these bits latched on sof if vcat.tlcr1.atmstd4 =1.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 250 of 375 register name: vcat.tcr3 register description: vcat transmit control register 3 register address: 420h (+ 002h x (n-1), physical wan port n=1 to 16) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 421h: - - - - tvsq3 tvsq2 tvsq1 tvsq0 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 420h: - - - tnvcgc tvgs2 tvgs1 tvgs0 tpa default 0 0 0 0 0 0 0 0 bits 8-11: transmit vcat sequence mapping (tvsq[3:0]) these four bits are a bcd number that is used in the ?sq? field of the vcat mfi on that port. when lcas is enabled, the internal lcas engine controls the transmit sequence number and reading these bits provides the current assigned sequence number for a given port. the user should take care to not overwrite these bits when lcas is enabled. when lcas is not enabled, the user can write a value to specifically assign a port?s sequence in a vcg. note that in t3/e3 operation, only sequence numbers 0-7 are valid. bit 4: transmit non-vcg control (tnvcgc) 0 = the vcat byte position is not used for pay load data. required when placing gfp encapsulated ethernet over pdh for comp liance with itu-t g.8040. 1 = the vcat byte position is used for payload data. only valid when the port is not configured as a member of a vcat group. bits 1-3: transmit port n vcat group selection (tvgs[2:0]) tvgs[2:0] transmit wan group and vcat selection 000 vcat disabled for wan port, wan group 1 001 vcat enabled for wan port, wan group 1 (vcg1) 010 vcat disabled for wan port, wan group 2 011 vcat enabled for wan port, wan group 2 (vcg2) 100 vcat disabled for wan port, wan group 3 101 vcat enabled for wan port, wan group 3 (vcg3) 110 vcat disabled for wan port, wan group 4 111 vcat enabled for wan port, wan group 4 (vcg4) note: only one port may be assigned to a non-vcg. bit 0: transmit port n assign (tpa) 0 = port n is unused. 1 = port n is assigned to a wan group or vcg.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 251 of 375 register name: vcat.tlcr8 register description: vcat transmit lcas control register 8 register address: 440h (+ 002h x (n-1), physical wan port n=1 to 16) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 441h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 440h: - - - - ctrl3 ctrl2 ctrl1 ctrl0 default 0 0 0 0 0 0 0 0 bits 0-3: port n control code (ctrl[3:0]). ctrl[3:0] control word 0000 fixed 0001 add 0010 norm 0011 eos 0101 idle 1111 dnu register name: vcat.tcr4 register description: vcat transmit control register 4 register address: 470h (+ 002h x (n-1), wan group n=1 to 4) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 471h: tgid15 tgid14 tgid13 tgid12 tgid11 tgid10 tgid9 tgid8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 470h: tgid7 tgid6 tgid5 tgid4 tgid3 tgid2 tgid1 tgid0 default 0 0 0 0 0 0 0 0 bits 12-15: transmit gid value (tgid[15:0]) these bits contain a user-programmed value to be transmitted through the vcat gid. one value is used for all members of each wan group. only used when vcat.tcr1.tgidm = 1.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 252 of 375 10.7.2 vcat receive r egister description note: some registers are on a per-wan-port basis. register name: vcat.rcr1 register description: vcat receive control register 1 register address: 500h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 501h: - - - rven4 rgidbc rven3 rven2 rven1 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 500h: - - svintd t3t1wg4 t3t1wg3 t3t1wg2 t3t1wg1 rvblken default 0 0 0 0 0 0 0 0 bit 12: receive vcat and data path enable for vcg 4 (rven4) data path reset and enable. this bit function is not available in device revision a1 ( gl.idr.revn=000). 0 = vcat block is disabled and held in reset; data path is disabled for receive wan group #4 1 = vcat block is enabled; data path is enabled for receive wan group #4 note: this bit must be set to enable the data path, even when operating in non-vcg modes bit 11: receive gid bit convention (rgidbc) controls all 4 vcgs. this bit is only used when tgidm = 1 0 = bit 15 of the rgidx register is received first. 1 = bit 0 of rgidx register is received first. bit 10: receive vcat and data path enable for vcg 3 (rven3) data path reset disable. this bit function is not available in device revision a1 ( gl.idr.revn=000). 0 = vcat block is disabled and held in reset; data path is disabled for receive wan group #3 1 = vcat block is enabled; data path is enabled for receive wan group #3 note: this bit must be set to enable the data path, even when operating in non-vcg modes bit 9: receive vcat and data path enable for vcg 2 (rven2) data path reset disable. this bit function is not available in device revision a1 ( gl.idr.revn=000). 0 = vcat block is disabled and held in reset; data path is disabled for receive wan group #2 1 = vcat block is enabled; data path is enabled for receive wan group #2 note: this bit must be set to enable the data path, even when operating in non-vcg modes bit 8: receive vcat and data path enable for vcg 1 (rven1) data path reset disable. this bit function is not available in device revision a1 ( gl.idr.revn=000). 0 = vcat block is disabled and held in reset; data path is disabled for receive wan group #1 1 = vcat block is enabled; data path is enabled for receive wan group #1 note: this bit must be set to enable the data path, even when operating in non-vcg modes bit 5: sequence value integration disable (svintd) integration of sequence values applies to non-lcas operation only. 0 = sequence value integrated is enabled. 1 = sequence value integration is disabled. bit 4: t3/e3 or t1/e1 selection for wan group 4 (t3t1wg4) 0 = device configured for t1/e1 vcgs 1 = device configured for t3/e3 vc gs (must be ports 1 to 8 only) bit 3: t3/e3 or t1/e1 selection for wan group 3 (t3t1wg3) 0 = device configured for t1/e1 vcgs 1 = device configured for t3/e3 vc gs (must be ports 1 to 8 only)
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 253 of 375 bit 2: t3/e3 or t1/e1 selection for wan group 2 (t3t1wg2) 0 = device configured for t1/e1 vcgs 1 = device configured for t3/e3 vc gs (must be ports 1 to 8 only) bit 1: t3/e3 or t1/e1 selection for wan group 1 (t3t1wg1) 0 = device configured for t1/e1 vcgs 1 = device configured for t3/e3 vc gs (must be ports 1 to 8 only) bit 0: receive vcat block enable (rvblken) data path reset disable. 0 = vcat block is disabled; data path is disabled 1 = vcat block is enabled; data path is enabled note: this bit must be set even in non-vcg modes
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 254 of 375 register name: vcat.rcr2 register description: vcat receive control register 2 register address: 502h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 503h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 502h: le4 le3 le2 le1 realign4 realign3 realign2 realign1 default 0 0 0 0 0 0 0 0 bit 7: lcas enable vcg4 (le4). 0 = vcg 4 is not enabled for lcas 1 = vcg 4 is enabled for lcas bit 6: lcas enable vcg 3 (le3). 0 = vcg 3 is not enabled for lcas 1 = vcg 3 is enabled for lcas bit 5: lcas enable vcg 2 (le2). 0 = vcg 2 is not enabled for lcas 1 = vcg 2 is enabled for lcas bit 4: lcas enable vcg 1 (le1). 0 = vcg 1 is not enabled for lcas 1 = vcg 1 is enabled for lcas bits 0-3: manual re-alignment of vcat members for vcgn (realign[4:1]) a 0-to-1 transition of this bit causes the re-alignment state machine for vcgn to restart.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 255 of 375 register name: vcat.rcr3 register description: vcat receive control register 3 register address: 504h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 505h: rv4mc3 rv4mc2 rv4mc1 rv4mc0 rv3mc3 rv3mc2 rv3mc1 rv3mc0 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 504h: rv2mc3 rv2mc2 rv2mc1 rv2mc0 rv1mc3 rv1mc2 rv1mc1 rv1mc0 default 0 0 0 0 0 0 0 0 bits 12-15: receive vcg4 member count (rv4mc[3:0]) these bits indicate to the device the number of members assigned to vcg4. 0000 = 1 member 0001 = 2 members 0010 = 3 members ?.. 1111 = 16 members note: this count represents all members of a vcg, active or not. bits 8-11: receive vcg3 member count (rv3mc[3:0]) these bits indicate to the device the number of members assigned to vcg3. 0000 = 1 member 0001 = 2 members 0010 = 3 members ?.. 1111 = 16 members note: this count represents all members of a vcg, active or not. bits 4-7: receive vcg2 member count (rv2mc[3:0]) these bits indicate to the device the number of members assigned to vcg2. 0000 = 1 member 0001 = 2 members 0010 = 3 members ?.. 1111 = 16 members note: this count represents all members of a vcg, active or not. bits 0-3: receive vcg1 member count (rv1mc[3:0]) these bits indicate to the device the number of members assigned to vcg1. 0000 = 1 member 0001 = 2 members 0010 = 3 members ?.. 1111 = 16 members note: this count represents all members of a vcg, active or not.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 256 of 375 register name: vcat.risr register description: vcat receive interrupt status register register address: 508h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 509h: pisr16 pisr15 pisr14 pisr13 pisr12 pisr11 pisr10 pisr9 default 1 1 1 1 1 1 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 508h: pisr8 pisr7 pisr6 pisr5 pisr4 pisr3 pisr2 pisr1 default 1 1 1 1 1 1 1 1 bits 0-15: vcat port interrupt status (pisr[16:1]) this bit is set when the corresponding serial port?s receive serial status latched register ( vcat.rslsr[1-16] ) has one or more bits set and its corresponding interrupt enable bit is also set. register name: vcat.rlsr1 register description: vcat receive lcas status register 1 register address: 50ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 50bh: v1mst15 v1mst14 v1mst13 v1mst12 v1mst11 v1mst10 v1mst9 v1mst8 default 1 1 1 1 1 1 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 50ah: v1mst7 v1mst6 v1mst5 v1mst4 v1mst3 v1mst2 v1mst1 v1mst0 default 1 1 1 1 1 1 1 1 bits 0-15: v1mst[15:0] vcg1 mst status 0 = member n receives mst = ok 1 = member n receives mst = ok note: on reset, this register will be set to all ones
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 257 of 375 register name: vcat.rlsr2 register description: vcat receive lcas status register 2 register address: 50ch bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 50dh: v2mst15 v2mst14 v2mst13 v2mst12 v2mst11 v2mst10 v2mst9 v2mst8 default 1 1 1 1 1 1 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 50ch: v2mst7 v2mst6 v2mst5 v2mst4 v2mst3 v2mst2 v2mst1 v2mst0 default 1 1 1 1 1 1 1 1 bits 0-15: v2mst[15:0] vcg2 mst status 0 = member n receives mst = ok 1 = member n receives mst = ok note: on reset, this register will be set to all ones register name: vcat.rlsr3 register description: vcat receive lcas status register 3 register address: 50eh bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 50fh: v3mst15 v3mst14 v3mst13 v3mst12 v3mst11 v3mst10 v3mst9 v3mst8 default 1 1 1 1 1 1 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 50eh: v3mst7 v3mst6 v3mst5 v3mst4 v3mst3 v3mst2 v3mst1 v3mst0 default 1 1 1 1 1 1 1 1 bits 0-15: v3mst[15:0] vcg3 mst status 0 = member n receives mst = ok 1 = member n receives mst = ok note: on reset, this register will be set to all ones
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 258 of 375 register name: vcat.rlsr4 register description: vcat receive lcas status register 4 register address: 510h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 511h: v4mst15 v4mst14 v4mst13 v4mst12 v4mst11 v4mst10 v4mst9 v4mst8 default 1 1 1 1 1 1 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 510h: v4mst7 v4mst6 v4mst5 v4mst4 v4mst3 v4mst2 v4mst1 v4mst0 default 1 1 1 1 1 1 1 1 bits 0-15: v4mst[15:0] vcg4 mst status 0 = member n sends mst = ok 1 = member n sends mst = fail note: default upon power-up is all ones. these bits latched on sof if vcat.tlcr1.atmstd4 =1. register name: vcat.rrlsr register description: vcat receive realign latched status register register address: 512h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 513h: - - - - vmstc4 vmstc3 vmstc2 vmstc1 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 512h: dde4 dde3 dde2 dde1 realignl4 realignl3 realignl2 realignl1 default 0 0 0 0 0 0 0 0 bits 8-11: mst change on vcgn (vmstc[4:1] this bit is set when any of the 16 mst bits associated with vcgn have changed value. bits 4-7: differential delay exceeded on vcgn this bit is set when the delay between members of the corresponding vcg has exceeded the tolerance. when set, wan traffic from the vcg will not be forwarded to the lan port. bits 0-3: receive re-alignment of vcgn (realignl[4:1]) this bit is set when the corresponding realignment state machine completes successfully.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 259 of 375 register name: vcat.rrsie register description: vcat receive realign status interrupt enable register address: 514h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 515h: - - - - vmstcie4 vmstcie3 vmstcie2 vmstcie1 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 514h: ddeie4 ddeie3 ddeie2 ddeie1 realignie4 realignie3 realignie2 realignie1 default 0 0 0 0 0 0 0 0 bit 11: vcg4 mstc change in terrupt enable (vmstcie4) this bit enables an interrupt if vmstc4 is set. bit 10: vcg3 mstc change in terrupt enable (vmstcie3) this bit enables an interrupt if vmstc3 is set. bit 9: vcg2 mstc change in terrupt enable (vmstcie2) this bit enables an interrupt if vmstc2 is set. bit 8: vcg1 mstc change in terrupt enable (vmstcie1) this bit enables an interrupt if vmstc1 is set. bit 7: vcg4 differential delay exceeded interrupt enable (ddeie4). this bit enables an interrupt for dde4. bit 6: vcg3 differential delay exceeded interrupt enable (ddeie3). this bit enables an interrupt for dde3. bit 5: vcg2 differential delay exceeded interrupt enable (ddeie2). this bit enables an interrupt for dde2. bit 4: vcg1 differential delay exceeded interrupt enable (ddeie1). this bit enables an interrupt for dde1. bits 0-3: receive re-alignment of vcgn interrupt enable (realignie[4:1]) this bit enables an interrupt if the corresponding realignln bit is set. 0 = interrupt disabled 1 = interrupt enabled
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 260 of 375 register name: vcat.rcr4 register description: vcat receive control register 4 register address: 530h (+ 002h x (n-1), physical wan port n=1 to 16) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 531h: rfrst - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 530h: rfm - - rnvcgc rvgs2 rvgs1 rvgs0 rpa default 0 0 0 0 0 0 0 0 bit 15: receive fifo reset (rfrst) 0 = the receive fifo resumes normal operations 1 = the receive fifo is in reset. the fifo is emptied, any transfer in progress is halted, the fifo circuit is powered down. bit 7: remove and reframe (rfm) a zero-to-one transition of this bit forces the associated line into the ?removed? state, which is held as long as the bit remain s a 1. a one-to-zero transition on this bit causes the associated receive port to re frame on the vcat overhead. bit 4: receive non-vcg control (rnvcgc) 0 = the vcat byte position is not used for payload data. 1 = the vcat byte position is used for payload data. only valid when the port is not configured as a member of a vcat group. bits 1-3: receive port n vcat group selection (rvgs[2:0]) rvgs[2:0] receive wan group and vcg selection 000 vcat disabled for wan port, wan group 1 001 vcat enabled for wan port, wan group 1 (vcg1) 010 vcat disabled for wan port, wan group 2 011 vcat enabled for wan port, wan group 2 (vcg2) 100 vcat disabled for wan port, wan group 3 101 vcat enabled for wan port, wan group 3 (vcg3) 110 vcat disabled for wan port, wan group 4 111 vcat enabled for wan port, wan group 4 (vcg4) note: only a single wan port may be assigned to a wan group in which vcat is disabled. bit 0: receive port n assign (rpa) 0 = port n is unassigned. 1 = port n is assigned to a vcg or non-vcg.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 261 of 375 register name: vcat.rsr1 register description: vcat receive status register 1 register address: 550h (+ 002h x (n-1), physical wan port n=1 to 16) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 551h: rvsq3 rvsq2 rvsq1 rvsq0 ctrl3 ctrl2 ctrl1 ctrl0 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 550h: - - - rsack - - - lom default 0 0 0 0 0 0 0 0 bits 12-15: port n receive sequence (rvsq[3:0]) these bits are updated every vcat frame on sof boundaries. these bits report the previous frame?s sequence value. (lcas only) bits 8-11: port n control word (ctrl[3:0]) these bits are updated every vcat frame on sof boundaries. these bits report the previous frame?s control word. (lcas only) ctrl[3:0] control word 0000 fixed 0001 add 0010 norm 0011 eos 0101 idle 1111 dnu bit 4: rs-ack status (rsack) 0 = rs-ack for port n for the previous vcat frame is 0. 1 = rs-ack for port n for the previous vcat frame is 1. bit 0: loss of multiframe sync (lom) ? this bit corresponds to the receive vcat framer status of the wan port. 0 = no lom for port n 1 = lom active for port n
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 262 of 375 register name: vcat.rsr2 register description: vcat receive status register 2 register address: 570h (+ 002h x (n-1), physical wan port n=1 to 16) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 571h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 570h: - - - - crce gid semf emf default 0 0 0 0 0 0 1 0 bit 3: crc error (crce) this status bit is set if there was a crc e rror in the previous vcat frame. (lcas only) bit 2: gid alarm (gid) this status bit is set if the gid of port n does not match the vcg?s gid value. bit 1: severely errored multiframe (semf) this status bit is set if there were 4 or more mfi errors in the previous multiframe. updated on multiframe boundaries. bit 0: errored multiframe (emf) this status bit is set if there was at least one mfi error in the previous multiframe. updated on multiframe boundaries. register name: vcat.rslsr register description: vcat receive serial latched status register register address: 590h (+ 002h x (n-1), physical wan port n=1 to 16) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 591h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 590h: - - - rsackl sql ctrl - loml default 0 0 0 0 0 0 0 0 bit 4: rs-ack change latched (rsackl) set when the corresponding rsac k status bit changes state. bit 3: sq change latched (sql) set when the sq[3:0] status bits change. bit 2: ctrl code change latched (ctrll) set when the ctrl[3:0] status bits change. bit 0: loss of multiframe sync change latched (loml) set when the corresponding lom bit changes from an inactive (0) to an active (1) state. the user should poll lom to determine when the lom condition is cleared.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 263 of 375 register name: vcat.rsie register description: vcat receive serial interrupt enable register register address: 5b0h (+ 002h x (n-1), physical wan port n=1 to 16) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 5b1h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5b0h: - - - rsackie sqie ctrie - lomie default 0 0 0 0 0 0 0 0 bit 4: rsack change inte rrupt enable (rsackie) this bit enables an interrupt if the rsackl bit is set. 0 = interrupt for port n is masked 1 = interrupt for port n is enabled bit 3: sq change inte rrupt enable (sqie) this bit enables an interrupt if the sql bit is set. 0 = interrupt for port n is masked 1 = interrupt for port n is enabled bit 2: ctrl change interrupt enable (ctrie) this bit enables an interrupt if the ctrll bit is set. 0 = interrupt for port n is masked 1 = interrupt for port n is enabled bit 0: loss of multiframe sync chan ge interrupt enable (lomie[16:1]) this bit enables an interrupt if the loml bit is set. 0 = interrupt for port n is masked 1 = interrupt for port n is enabled
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 264 of 375 register name: vcat.rsr3 register description: vcat receive status register 3 register address: 5d0h (+ 002h x (n-1), physical wan port n=1 to 16) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 5d1h: rgid15 rgid14 rgid13 rgid12 rgid11 rgid10 rgid9 rgid8 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 5d0h: rgid7 rgid6 rgid5 rgid4 rgid3 rgid2 rgid1 rgid0 default 0 0 0 0 0 0 0 0 bits 0 -15: receive gid (rgid[15:0]) these bits provide the received 16-bi t gid value for each of the 16 wan lines. latches the first bit when mfi2 = xxxx_0000. bit order is reversed if rgidbc=1.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 265 of 375 10.8 serial interface registers the serial interface contains the serial transport circui try and the associated serial port. the serial interface register map consists of register s that are common functions, transm it functions, and receive functions. bits that are underlined are read-only; all other bits can be writt en. all reserved registers and bits with ?-? designation should be written to zero, unless specifically not ed in the register definition. when read, the information from reserved registers and bits de signated with ?-? should be discarded. counter registers are updated by asserting (low to hi gh transition) the associated performance monitoring update signal (xxpmu). during the counter register update proc ess, the associated performa nce monitoring status signal (xxpms) is deasserted. the counter r egister update process consists of lo ading the counter register with the current count, resetting the counter, forcing the zero count status indication low for one clock cycle, and then asserting xxpms. no events are miss ed during this update procedure. a latched bit is set when the associated event occurs, and re mains set until it is cleared by reading. once cleared, a latched bit will not be set again until the associated event occurs again. reserved confi guration bits and registers should be written to zero. 10.8.1 serial interface tr ansmit and common registers serial interface transmit registers are used to control t he transmitter associated with each serial interface. the register map is shown in the following table. note that throughout this document the hdlc processor is also referred to as a ? packet processor?. 10.8.2 serial interface transmit register bit descriptions register name: li.lcr1 register description: serial interface loopback control register 1 register address: 600h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 601h: llb16 llb15 llb14 llb13 llb12 llb11 llb10 llb9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 600h: llb8 llb7 llb6 llb5 llb4 llb3 llb2 llb1 default 0 0 0 0 0 0 0 0 bits 0-15: line loopback enable (llb[15:0]) data received on rdatan will be looped to the transmit serial port, replacing the data on tdatan. (not e: tclkn must be the same clock as rclkn). 0 = line loopback is disabled 1 = line loopback is enabled
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 266 of 375 register name: li.lcr2 register description: serial interface loopback control register 2 register address: 602h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 603h: tlb16 tlb15 tlb14 tlb13 tlb12 tlb11 tlb10 tlb9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 602h: tlb8 tlb7 tlb6 tlb5 tlb4 tlb3 tlb2 tlb1 default 0 0 0 0 0 0 0 0 bits 0-15: terminal loopback enable(tlb[16:1]). data transmitted on tdatan will be internally looped to the receive serial port and data on rdatan will be ignored and tclkn will replace rclkn. 0 = terminal loopback is disabled 1 = terminal loopback is enabled register name: li.tcsr register description: serial interface transmit clock status register register address: 604h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 605h: - - - tmclka4 - - - tmclka3 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 604h: tclka8 tclka7 tclka6 tclka5 tclka4 tclka3 tclka2 tclka1 default 0 0 0 0 0 0 0 0 bit 12: transmit clock active (tmclka4). 0 = tmclk4 is not transitioning. 1 = tmclk4 is active. note: this real-time status bit reports w hether tmclk4 has transitioned since the last read of this register. bit 8: transmit clock active (tmclka3). 0 = tmclk3 is not transitioning. 1 = tmclk3 is active. note: this real-time status bit reports w hether tmclk4 has transitioned since the last read of this register. bits 0-7: transmit clock active (tclka[8:1]) 0 = tmclkm/tclkn is not transitioning 1 = tmclkm/tclkn is active note: this real-time status bit reports whether tmclkm/tclkn has transitioned since the last read of this register.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 267 of 375 register name: li.tvcsr register description: serial interface transmit voice clock status register register address: 606h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 607h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 606h: - - - - - - - tvclka1 default 0 0 0 0 0 0 0 0 bit 0: transmit voice clock active (tclka1). 0 = tvclk1 is not transitioning 1 = tvclk1 is active note: this real-time status bit reports whether tvclka1 has transitioned since the last read of this register. register name: li.rcsr register description: serial interface receive clock status register register address: 608h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 609h: rclka16 rclka15 rclka14 rclka13 rclka12 rclka11 rclka10 rclka9 default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 608h: rclka8 rclka7 rclka6 rclka5 rclka4 rclka3 rclka2 rclka1 default 0 0 0 0 0 0 0 0 bits 0-15: receive clock active (rclka[16:1]) 0 = rclkn is not transitioning 1 = rclkn is active note: this real-time status bit reports whether rclkn has transitioned since the last read of this register.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 268 of 375 register name: li.rvcsr register description: serial interface receive vo ice clock status register register address: 60ah bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 60bh: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 60ah: - - - - - - - rvclka1 default 0 0 0 0 0 0 0 0 bit 0: receive voice clock active (rvclka1) 0 = rvclk is not transitioning 1 = rvclk is active note: this real-time status bit reports whether rvclk has transitioned since the last read of this register.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 269 of 375 10.8.3 transmit per serial port register description register name: li.tcr register description: serial interface transmit control register register address: 640h (+ 008h x (n-1), physical serial port n=1 to 16) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 641h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 640h: - - - tclkinv - ts_setup1 ts_setup0 td_sel default 0 0 0 0 0 0 0 0 bit 4: tmclkm/tclkn invert (tclkinv) note: valid for m = 1 to 4, n = 1 to 8. 0 = tmclkm/tclkn is not inverted 1 = tmclkm/tclkn is inverted bits 1-2: tsync setup (ts_setup[1:0]). these two bits accommodate a tsync signal that arrives earlier than the start of frame. ts_setup[1:0] tsync arrives 00 0 cycles early 01 1 cycle early 10 2 cycles early 11 3 cycles early bit 0: tdata select (td_sel). 0 = tdatan is referenced to the associated tmclkn, tmsyncn. 1 = tdatan is referenced to the associated tc lkn, tsyncn. not valid for serial ports 9-16. tmclkn / tmsyncn assignment when td_sel=0 ports tmclk1 / tmsync1 1-4 tmclk2 / tmsync2 5-8 tmclk3 / tmsync3* 9-12* tmclk4 / tmsync4* 13-16* * note: for serial ports 9-16, the td_sel bit is not available. ports 9-16 must use tmclkn and tmsyncn.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 270 of 375 10.8.4 transmit voice port register description register name: li.tvpcr register description: serial interface transmit voice port control register register address: 6c0h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 6c1h: - - - - - - tvfrst tvclki default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6c0h: tvopf4 tvopf3 tvopf2 tvopf1 tvopf0 tsyncc pc tpe default 0 0 0 0 0 0 0 0 bit 9: transmit voice fifo reset (tvfrst) 0 = the transmit voice fifo resumes normal operations 1 = transmit voice fifo reset. the fifo is emptied, any transfer in progress is hal ted, the fifo circuit is powered down, and all incoming data is discarded. bit 8: transmit voice clock invert (tvclki). 0 = tvclk is not inverted 1 = tvclk is inverted bits 3-7: transmit voice octets per frame (tvopf[4:0]). controls the number of octets that are used for voice traffic per frame. note: max. number of oc tets allowed to be used for voice is 16. 00001 = 1 st byte after frame sync is a voice channel. 00010 = 1 st two bytes after frame sync are voice channels bit 2: tsync control (tsyncc) this setting is necessary only if vo ice ports are enabled. tvsync must be a frame sync. 0 = tsync is a frame sync. voice bytes output to tdata from voice fifo after every tsync. 1 = tsync is a multiframe sync. voice output to tdata from voice fifo based on pc bit. bit 1: port configuration (pc) used to divide down multiframe sync to frame sync. 0 = port is configured for t1. 1 = port is configured for e1. bit 0: transmit port enable (tpe) 0 = port is disabled 1 = port is enabled
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 271 of 375 register name: li.tvfsr register description: serial interface transmit voice fifo status register register address: 6c2h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 6c3h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6c2h: - - - - - - tvfu tvfo default 0 0 0 0 0 0 0 0 bit 1: transmit voice fifo underflow (tvfu) this bit is set during a transmit voice fifo underflow. an underflow condition results in a loss of data. this bi t remains set as long as the underflow condition exists. bit 0: transmit voice fifo overflow (tvfo) ? this bit is set during a transmit voice fifo overflow. an overflow condition results in a loss of data. this bit rema ins set as long as the overflow condition exists. register name: li.tvflsr register description: serial interface transmit voice fifo latched status register register address: 6c4h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 6c5h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6c4h: - - - - - - tvful tvfol default 0 0 0 0 0 0 0 0 bit 1: transmit voice fifo underflow latched (tvful) this bit is set when a tr ansmit voice fifo underflow condition occurs. an underflow condition results in a loss of data. this bit remains set as long as the underflow condition exists. bit 0: transmit voice fifo overflow latched (tvfol) this bit is set when a transmit voice fifo overflow condition occurs. an overflow condition results in a loss of data. this bit remains set as long as the overflow condition exists.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 272 of 375 register name: li.tvfsrie register description: serial interface transmit voice fifo interrupt enable register register address: 6c8h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 6c9h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 6c8h: - - - - - - tvfulie tvfolie default 0 0 0 0 0 0 0 0 bit 1: transmit voice fifo unde rflow interrupt enable (tvfulie) this bit enables an interrupt if the tvful bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: transmit voice fifo over flow interrupt enable (tvfolie) ? this bit enables an interrupt if the tvfol bit is set . 0 = interrupt disabled 1 = interrupt enabled
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 273 of 375 10.8.5 receive per serial po rt register description register name: li.rcr1 register description: serial interface receive control register 1 register address: 740h (+ 008h x (n-1), physical serial port n=1 to 16) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 741h: - - - - - - - - default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 740h: - - - rclkinv - - rfrst - default 0 0 0 0 0 0 0 0 bit 4: rclkn invert (rclkinv) 0 = rclkn is not inverted, rdata samples on rising edge of rclk. 1 = rclkn is inverted, rdata samples on falling edge of rclk. bit 1: receive fifo reset (rfrst) 0 = the receive fifo resumes normal operations 1 = receive fifo reset. the fifo is emptied, any tr ansfer in progress is halted, the fifo circuit is powered down, the pointers are reset, and all incoming data is discarded. bit 0: reserved. set to 0 for proper operation.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 274 of 375 10.8.6 receive voice port register description register name: li.rvpcr register description: serial interface receive voice port control register register address: 7c0h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 7c1h: - - - - - - rvfrst rvclki default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 7c0h: rvopf4 rvopf3 rvopf2 rvopf1 rvopf0 rsyncc pc rpe default 0 0 0 0 0 0 0 0 bit 9: receive voice fifo reset (rvfrst) 0 = the receive voice fifo resumes normal operations 1 = receive voice fifo reset. the fifo is emptied, any transfer in progress is hal ted, the fifo circuit is powered down, and all incoming data is discarded. bit 8: receive voice clock invert (rvclki) 0 = rvclk is not inverted 1 = rvclk is inverted bits 3-7: receive voice octets per frame (rvopf[4:0]). controls the number of octets that are used for voice traffic per frame. note: max. number of oc tets allowed to be used for voice is 16. 00001 = 1 st byte after frame sync is a voice channel. 00010 = 1 st two bytes after frame sync are voice channels? bit 2: rsync control (rsyncc). this setting is necessary only if voice ports are enabled. rvsync must be a frame sync. 0 = rsync is a frame sync. voice bytes inse rted into voice fifo after every rsync. 1 = rsync is a multiframe sync. voice bytes inse rted into voice fifo based on pc register bit. bit 1: port configuration (pc). used to divide down multiframe sync to frame sync. 0 = port is configured for t1. 1 = port is configured for e1. bit 0: receive port enable (rpe) 0 = port is disabled 1 = port is enabled
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 275 of 375 10.8.7 mac registers the control registers related to the control of the individual macs are sh own in the following table. the device keeps statistics for the packet traffic sent and received. note that the address es listed are the indirect addresses that must be provided to su.mac1radh/ su.mac1radl or su.mac1awh/ su.mac1awl. register name: su.maccr register description: mac control register register address: 0000h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0000h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0001h: wdd jd fbe jfe reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0002h: gmiimiis em dro lm dm reserved drty apst default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0003h: acst bolmt1 bolmt0 dc te re reserved reserved default 0 0 0 0 0 0 0 0 bit 23: watchdog disable (wdd) - when set to 1, the watchdog timer on t he receiver is disabled. when equal to 0, the mac allows only 2048 bytes of data per frame. bit 22: jabber disable (jd) - when set to 1, the transmitter?s jabber timer is disabled. when equal to 0, the mac allows only 2048 bytes to be transmitter per frame. bit 21: frame burst enable (fbe) ? when set to 1, the mac allows fram e bursting during transmission in half- duplex mode. bit 20: jumbo frame enable (jfe) - when set to 1, the mac allows the reception of frames up to 9018 bytes in length without reporting a giant frame error in the re ceive frame status register. frames between 9018 and 10240 bytes in length are passed with a giant frame error indica tion. jabber disable and watchdog disable bits should be set to 1 to transmit and receive jumbo frames. this bi t should be cleared when operating in full-duplex mode. bit 15: gmii / mii selection (gmiimiis) 0 = gmii mode 1 = mii/rmii mode bit 14: endian mode (em) - when set to 1, the mac operates in bi g-endian mode. when equal to 0, the mac operates in little-endian mode. the endian mode selecti on is applicable only for the transmit and receive data paths. bit 13: disable receive own (dro) - when set to 1, the mac disables the reception of frames while tx_en is asserted. when this bit equals zero, transmitted frames ar e also received by the mac. this bit should be cleared when operating in full-duplex mode.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 276 of 375 bit 12: loopback mode (lm) - when set to 1, all frames destined for the transmit gmii/mii/rmii interface are internally transferred to the receive gmii/mii/rmii. frames received on the gmii/mii/rmii are not transferred to the transmit gmii/mii/rmii interface. note that there is no sa/da swapping performed. if sa/da swapping of lan traffic is required, the lan extract/insertion functions must be used. bit 11: duplex mode (dm) - when set to 1, the mac transmits and receives simultaneously (full-duplex). bit 9: disable retry (drty) - when set to 1, the mac makes only a si ngle attempt to transmit each frame. if a collision occurs, the mac ignores the cu rrent frame, reports a frame abort, reports an excessive collision error, and proceeds to the next frame. when this bit equals 0, t he mac will retry collided frames based on the settings in the backoff limit bits before signaling a retry erro r. this bit is applicable to half-duplex mode only. bit 8: automatic pad stripping (apst) - when set to 1, all incoming frames with less than 46 byte length are automatically stripped of t he pad characters and fcs. when equal to zero, all frames are received unmodified. bit 7: automatic crc stripping (acst) - when set to 1, the mac will strip the fcs field on incoming frames only if the length field is less than or equal to 1500 bytes. all received frames with length field greater than 1500 bytes will be passed to the receiver without stripping of the fcs field. when equal to zero, all frames are received unmodified. for most applications of this device, this bit should equal 0. bits 5 - 6: back-off limit (bolmt[1:0])- these two bits allow the user to set the back-off limit used for the maximum retransmission delay for collided frames. defaul t operation limits the maximum delay for retransmission to a countdown of 10 bits from a random number generator. the user can reduce the maximum number of counter bits as described in the table below. see i eee 802.3 for details of the back-off algorithm. bit 7 bit 6 random number generator bits used 0 0 10 0 1 8 1 0 4 1 1 1 bit 4: deferral check (dc) - when set to 1, the mac will abort frame tr ansmission if it has deferred for more than 24,288 bit times. the deferral counter starts when the trans mitter is ready to transmit a frame, but is prevented from transmission because rx_crs is active. if the ma c begins transmission but a collision occurs after the beginning of transmission, the deferral counter is reset again. if this bit is equal to zero, then the mac will defer indefinitely. bit 3: transmitter enable (te) - when set to 1, frame transmission is enabled. when equal to zero, transmission is disabled. bit 2: receiver enable (re) - when set to 1, frame reception is enabled. when equal to zero, frames are not received.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 277 of 375 register name: su.macffr register description: mac frame filter register register address: 0004h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0004h: raf reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0005h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0006h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0007h: pcf reserve d dbf pam invf hfuf hfmf pm default 0 0 0 0 0 0 0 0 bit 31: receive all frames (raf) - when set to 1, the receiver forwards a ll frames to the device, even if they do not pass the destination address filter. when equal to zero, the receiver only forwards those frames that pass the destination address filter. bit 7: pass pause control frames (pcf) - when set to 1, the receiver forwards all special multicast pause control frames to the device. the mac also decodes t he pause control frame and disables the transmitter for the specified amount of time. when equal to zero, the mac decodes the pause control frame and disables the transmitter for the specified amount of time, but does not forward the pause frame to the device. bit 5: disable broadcast frames (dbf) - when set to 1, the mac filters all incoming broadcast frames. when equal to zero, all broadcast frames are forwarded to the device. bit 4: pass all multicast (pam) - when set to 1, all received multicast frames (1 st bit of da = ?1?) are forwarded, irrespective of the settings of the hash filter and inverse filtering bits. bit 3: inverse filtering (invf) - when set to 1, the programmable da filter operates in inverse filtering mode. the result of the filtering operations by the hash hfuf/hfmf bits is inverted. when equal to zero, filtering is determined by the hfuf/hfmf bits. bit 2: hash mode for unicast frames (hfuf) - when set to 1, address filtering operates in the imperfect (hash) address filtering mode for unicast frames, according to the hash table. when equal to zero, perfect address filtering is performed on unicast frames using the addresses specified in the mac add ress filter registers. bit 1: hash mode for multicast frames (hfmf) - when set to 1, address filtering operates in the imperfect (hash) address filtering mode for multicast frames, according to t he hash table. when this bit equals zero, perfect address filtering is performed on multicast frames using the a ddresses specified in the mac address filter registers. bit 0: promiscuous mode (pm) ? when set to 1, all non-control frames are allowed to pass, including broadcast frames, regardless of destination address. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 278 of 375 register name: su.machthr register description: mac hash table high register register address: 0008h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0008h: hth[31] hth[30] hth[29] hth[28] hth[27] hth[26] hth[25] hth[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0009h: hth[23] hth[22] hth[21] hth[20] hth[19] hth[18] hth[17] hth[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 000ah: hth[15] hth[14] hth[13] hth[12] hth[11] hth[10] hth[9] hth[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000bh: hth[7] hth[6] hth[5] hth[4] hth[3] hth[ 2] hth[1] hth[0] default 0 0 0 0 0 0 0 0 bits 0-31: hash table high (hth[31:0]) - contains the upper 32 bits of the hash table used for group address filtering. register name: su.machtlr register description: mac hash table low register register address: 000ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 000ch: htl[31] htl[30] htl[29] htl[28] htl[27] htl[26] htl[25] htl[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 000dh: htl[23] htl[22] htl[21] htl[20] htl[19] htl[18] htl[17] htl[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 000eh: htl[15] htl[14] htl[13] htl[12] htl[11] htl[10] htl[9] htl[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000fh: htl[7] htl[6] htl[5] htl[4] htl[3] htl[2] htl[1] htl[0] default 0 0 0 0 0 0 0 0 bits 0-31: hash table low (htl[31:0]) - contains the upper 32 bits of the hash table used for group address filtering.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 279 of 375 register name: su.gmiia register description: mac mdio management address register register address: 0010h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0010h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0011h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0012h: ppa[4] ppa[3] ppa[2] ppa[1] ppa[0] gm[4] gm[3] gm[2] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0013h: gm[1] gm[0] reserved reserved cr[1] cr[0] gw gb default 0 0 0 0 0 0 0 0 bits 10-15: phy physical layer address (ppa[4:0]) - contains the address of the phy to be accessed. bits 6-9: phy mdio register (gm[4:0]) - contains the address of register within the phy to be accessed. bits 2-3: clock range (cr[1:0]) - selects mdc clock frequency. 00 = divide input clock by 42 01 = divide input clock by 62 10 = divide input clock by 16 11 = divide input clock by 26 bit 1: phy mdio write (gw) - when set to 1, a write operation will be performed. when equal to zero, a read operation will be performed. bit 0: phy gmii busy (gb) - this bit should be set to 1 when writing to su.gmiia. the mac will clear the bit when it is no longer busy. do not write to gmiia or gmiid while this bit is still set to 1. during read operations, the data in su.gmiid is invalid until this bit is equal to 0.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 280 of 375 register name: su.gmiid register description: mac mdio management data register register address: 0014h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0014h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0015h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0016h: gd[15] gd[14] gd[13] gd[12] gd[11] gd[10] gd[9] gd[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0017h: gd[7] gd[6] gd[5] gd[4] gd[3] gd[2] gd[1] gd[0] default 0 0 0 0 0 0 0 0 bits 0-15: mdio data (gd[15:0]) - contains the 16-bit value read from the phy after a management read operation, or the 16-bit value to be written during a write operation.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 281 of 375 register name: su.macfcr register description: mac flow control register register address: 0018h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0018h: pt[15] pt[14] pt[13] pt[12] pt[11] pt[10] pt[9] pt[8] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0019h: pt[7] pt[6] pt[5] pt[4] pt[3] pt[2] pt[1] pt[0] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 001ah: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 001bh: reserved reserve d reserved plt up rfe tfe fcb default 0 0 0 0 0 0 0 0 bits 16-31: pause time (pt[15:0]) - contains the 16-bit value to be used in the time field in transmitted pause control frames. bit 4: pause low threshold (plt) - set to 1 for 1000mbps operation. s hould equal 0 for 10/100mbps operation. recommended settings for pt and plt. pt[0:15] plt retransmit rate application value time value time 1 pause every 10mbps 176 slots 9.01ms 0 7.37ms 1.64ms 100mbps 176 slots 901 s 0 737 s 164 s 1gbps (mpl <2049) 44 slots 90.1 s 1 73.7 s 16.4 s 1gbps (mpl > 2048) 72 slots 147 s 1 131 s 16.4 s notes: ?slots? are defined by the ieee as the amount of time that it takes to transmit 64 bytes for 10/100mbps and 512 bytes for 1000mbps. only the 10/100mbps applications are applicable for the port 2 mac. bit 3: unicast pause frame detect (up) - when set to 1, the mac will detec t pause control frames with the device?s unicast address, in addition to detecting pause c ontrol frames with a multicast address. when equal to zero, the mac will only detect pause control frames with the unique multicast address as specified in the 802.3x standard. bit 2: receive flow control enable (rfe) - when set to 1, the mac will re ceive pause control frames and disable the transmitter for the specified pause time. when this bit is equ al to zero, the device will not respond to pause control frames. bit 1: transmit flow control enable (tfe) - when operating in full-duplex mode, if this bit is set, the mac will transmit pause control frames as needed. when equal to zero, the mac will not transmit pause control frames. bit 0: flow control busy (fcb) - this bit is equal to 1 when the transmi ssion of a pause control frame is in progress. if the user writes a ?1 ? to this bit, the device will tran smit one pause control frame.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 282 of 375 register name: su.vlantr register description: mac vlan tag register register address: 001ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 001ch: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 001dh: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 001eh: vltid[15] vltid[14] vltid[13] vltid[12] vltid[11] vltid[10] vltid[9] vltid[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 001fh: vltid[7] vltid[6] vltid[5] vltid[4] vltid[3] vltid[2] vltid[1] vltid[0] default 0 0 0 0 0 0 0 0 bits 0-15: vlan tag id (vltid[15:0]) - potentially not needed. d uplicated in other areas.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 283 of 375 register name: su.addr0h register description: mac filter address 0 high register address: 0040h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0040h: maddr0ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0041h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0042h: maddr0[47] maddr0[46] maddr0[45] maddr0[44] maddr0[43] maddr0[42] maddr0[41] maddr0[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0043h: maddr0[39] maddr0[38] maddr0[37] maddr0[36] maddr0[35] maddr0[34] maddr0[33] maddr0[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 0 enable (maddr0ae) - must be set to 1 if address filtering is enabled. bits 0-15: mac address filter 0 (maddr0[47:32]) - highest two bytes of mac filter address 0. register name: su.addr0l register description: mac filter address 0 low register address: 0044h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0044h: maddr0[31] maddr0[30] maddr0[29] maddr0[28] maddr0[27] maddr0[26] maddr0[25] maddr0[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0045h: maddr0[23] maddr0[22] maddr0[21] maddr0[20] maddr0[19] maddr0[18] maddr0[17] maddr0[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0046h: maddr0[15] maddr0[14] maddr0[13] maddr0[12] maddr0[11] maddr0[10] maddr0[9] maddr0[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0047h: maddr0[7] maddr0[6] maddr0[5] maddr0[4] maddr0[3] maddr0[2] maddr0[1] maddr0[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 0 (maddr0[31:0]) - lowest four bytes of mac filter address 0. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 284 of 375 register name: su.addr1h register description: mac filter address 1 high register address: 0048h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0048h: maddr1ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0049h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 004ah: maddr1[47] maddr1[46] maddr1[45] maddr1[44] maddr1[43] maddr1[42] maddr1[41] maddr1[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 004bh: maddr1[39] maddr1[38] maddr1[37] maddr1[36] maddr1[35] maddr1[34] maddr1[33] maddr1[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 1 enable (maddr1ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 1 (maddr1[47:32]) - highest two bytes of mac filter address 1. register name: su.addr1l register description: mac filter address 1 low register address: 004ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 004ch: maddr1[31] maddr1[30] maddr1[29] maddr1[28] maddr1[27] maddr1[26] maddr1[25] maddr1[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 004dh: maddr1[23] maddr1[22] maddr1[21] maddr1[20] maddr1[19] maddr1[18] maddr1[17] maddr1[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 004eh: maddr1[15] maddr1[14] maddr1[13] maddr1[12] maddr1[11] maddr1[10] maddr1[9] maddr1[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 004fh: maddr1[7] maddr1[6] maddr1[5] maddr1[4] maddr1[3] maddr1[2] maddr1[1] maddr1[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 1 (maddr1[31:0]) - lowest four bytes of mac filter address 1. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 285 of 375 register name: su.addr2h register description: mac filter address 2 high register address: 0050h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0050h: maddr2ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0051h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0052h: maddr2[47] maddr2[46] maddr2[45] maddr2[44] maddr2[43] maddr2[42] maddr2[41] maddr2[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0053h: maddr2[39] maddr2[38] maddr2[37] maddr2[36] maddr2[35] maddr2[34] maddr2[33] maddr2[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 2 enable (maddr2ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 2 (maddr2[47:32]) - highest two bytes of mac filter address 2. register name: su.addr2l register description: mac filter address 2 low register address: 0054h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0054h: maddr2[31] maddr2[30] maddr2[29] maddr2[28] maddr2[27] maddr2[26] maddr2[25] maddr2[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0055h: maddr2[23] maddr2[22] maddr2[21] maddr2[20] maddr2[19] maddr2[18] maddr2[17] maddr2[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0056h: maddr2[15] maddr2[14] maddr2[13] maddr2[12] maddr2[11] maddr2[10] maddr2[9] maddr2[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0057h: maddr2[7] maddr2[6] maddr2[5] maddr2[4] maddr2[3] maddr2[2] maddr2[1] maddr2[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 2 (maddr2[31:0]) - lowest four bytes of mac filter address 2. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 286 of 375 register name: su.addr3h register description: mac filter address 3 high register address: 0058h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0058h: maddr3ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0059h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 005ah: maddr3[47] maddr3[46] maddr3[45] maddr3[44] maddr3[43] maddr3[42] maddr3[41] maddr3[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 005bh: maddr3[39] maddr3[38] maddr3[37] maddr3[36] maddr3[35] maddr3[34] maddr3[33] maddr3[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 3 enable (maddr3ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 3 (maddr3[47:32]) - highest two bytes of mac filter address 3. register name: su.addr3l register description: mac filter address 3 low register address: 005ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 005ch: maddr3[31] maddr3[30] maddr3[29] maddr3[28] maddr3[27] maddr3[26] maddr3[25] maddr3[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 005dh: maddr3[23] maddr3[22] maddr3[21] maddr3[20] maddr3[19] maddr3[18] maddr3[17] maddr3[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 005eh: maddr3[15] maddr3[14] maddr3[13] maddr3[12] maddr3[11] maddr3[10] maddr3[9] maddr3[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 005fh: maddr3[7] maddr3[6] maddr3[5] maddr3[4] maddr3[3] maddr3[2] maddr3[1] maddr3[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 3 (maddr3[31:0]) - lowest four bytes of mac filter address 3. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 287 of 375 register name: su.addr4h register description: mac filter address 4 high register address: 0060h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0060h: maddr4ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0061h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0062h: maddr4[47] maddr4[46] maddr4[45] maddr4[44] maddr4[43] maddr4[42] maddr4[41] maddr4[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0063h: maddr4[39] maddr4[38] maddr4[37] maddr4[36] maddr4[35] maddr4[34] maddr4[33] maddr4[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 4 enable (maddr4ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 4 (maddr4[47:32]) - highest two bytes of mac filter address 4. register name: su.addr4l register description: mac filter address 4 low register address: 0064h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0064h: maddr4[31] maddr4[30] maddr4[29] maddr4[28] maddr4[27] maddr4[26] maddr4[25] maddr4[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0065h: maddr4[23] maddr4[22] maddr4[21] maddr4[20] maddr4[19] maddr4[18] maddr4[17] maddr4[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0066h: maddr4[15] maddr4[14] maddr4[13] maddr4[12] maddr4[11] maddr4[10] maddr4[9] maddr4[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0067h: maddr4[7] maddr4[6] maddr4[5] maddr4[4] maddr4[3] maddr4[2] maddr4[1] maddr4[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 4 (maddr4[31:0]) - lowest four bytes of mac filter address 4. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 288 of 375 register name: su.addr5h register description: mac filter address 5 high register address: 0068h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0068h: maddr5ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0069h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 006ah: maddr5[47] maddr5[46] maddr5[45] maddr5[44] maddr5[43] maddr5[42] maddr5[41] maddr5[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 006bh: maddr5[39] maddr5[38] maddr5[37] maddr5[36] maddr5[35] maddr5[34] maddr5[33] maddr5[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 5 enable (maddr5ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 5 (maddr5[47:32]) - highest two bytes of mac filter address 5. register name: su.addr5l register description: mac filter address 5 low register address: 006ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 006ch: maddr5[31] maddr5[30] maddr5[29] maddr5[28] maddr5[27] maddr5[26] maddr5[25] maddr5[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 006dh: maddr5[23] maddr5[22] maddr5[21] maddr5[20] maddr5[19] maddr5[18] maddr5[17] maddr5[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 006eh: maddr5[15] maddr5[14] maddr5[13] maddr5[12] maddr5[11] maddr5[10] maddr5[9] maddr5[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 006fh: maddr5[7] maddr5[6] maddr5[5] maddr5[4] maddr5[3] maddr5[2] maddr5[1] maddr5[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 5 (maddr5[31:0]) - lowest four bytes of mac filter address 5. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 289 of 375 register name: su.addr6h register description: mac filter address 6 high register address: 0070h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0070h: maddr6ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0071h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0072h: maddr6[47] maddr6[46] maddr6[45] maddr6[44] maddr6[43] maddr6[42] maddr6[41] maddr6[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0073h: maddr6[39] maddr6[38] maddr6[37] maddr6[36] maddr6[35] maddr6[34] maddr6[33] maddr6[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 6 enable (maddr6ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 6 (maddr6[47:32]) - highest two bytes of mac filter address 6. register name: su.addr6l register description: mac filter address 6 low register address: 0074h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0071h: maddr6[31] maddr6[30] maddr6[29] maddr6[28] maddr6[27] maddr6[26] maddr6[25] maddr6[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0072h: maddr6[23] maddr6[22] maddr6[21] maddr6[20] maddr6[19] maddr6[18] maddr6[17] maddr6[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0073h: maddr6[15] maddr6[14] maddr6[13] maddr6[12] maddr6[11] maddr6[10] maddr6[9] maddr6[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0074h: maddr6[7] maddr6[6] maddr6[5] maddr6[4] maddr6[3] maddr6[2] maddr6[1] maddr6[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 6 (maddr6[31:0]) - lowest four bytes of mac filter address 6. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 290 of 375 register name: su.addr7h register description: mac filter address 7 high register address: 0078h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0078h: maddr7ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0079h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 007ah: maddr7[47] maddr7[46] maddr7[45] maddr7[44] maddr7[43] maddr7[42] maddr7[41] maddr7[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 007bh: maddr7[39] maddr7[38] maddr7[37] maddr7[36] maddr7[35] maddr7[34] maddr7[33] maddr7[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 7 enable (maddr7ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 7 (maddr7[47:32]) - highest two bytes of mac filter address 7. register name: su.addr7l register description: mac filter address 7 low register address: 007ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 007ch: maddr7[31] maddr7[30] maddr7[29] maddr7[28] maddr7[27] maddr7[26] maddr7[25] maddr7[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 007dh: maddr7[23] maddr7[22] maddr7[21] maddr7[20] maddr7[19] maddr7[18] maddr7[17] maddr7[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 007eh: maddr7[15] maddr7[14] maddr7[13] maddr7[12] maddr7[11] maddr7[10] maddr7[9] maddr7[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 007fh: maddr7[7] maddr7[6] maddr7[5] maddr7[4] maddr7[3] maddr7[2] maddr7[1] maddr7[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 7 (maddr7[31:0]) - lowest four bytes of mac filter address 7. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 291 of 375 register name: su.addr8h register description: mac filter address 8 high register address: 0080h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0080h: maddr8ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0081h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0082h: maddr8[47] maddr8[46] maddr8[45] maddr8[44] maddr8[43] maddr8[42] maddr8[41] maddr8[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0083h: maddr8[39] maddr8[38] maddr8[37] maddr8[36] maddr8[35] maddr8[34] maddr8[33] maddr8[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 8 enable (maddr8ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 8 (maddr8[47:32]) - highest two bytes of mac filter address 8. register name: su.addr8l register description: mac filter address 8 low register address: 0084h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0084h: maddr8[31] maddr8[30] maddr8[29] maddr8[28] maddr8[27] maddr8[26] maddr8[25] maddr8[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0085h: maddr8[23] maddr8[22] maddr8[21] maddr8[20] maddr8[19] maddr8[18] maddr8[17] maddr8[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0086h: maddr8[15] maddr8[14] maddr8[13] maddr8[12] maddr8[11] maddr8[10] maddr8[9] maddr8[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0087h: maddr8[7] maddr8[6] maddr8[5] maddr8[4] maddr8[3] maddr8[2] maddr8[1] maddr8[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 8 (maddr8[31:0]) - lowest four bytes of mac filter address 8. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 292 of 375 register name: su.addr9h register description: mac filter address 9 high register address: 0088h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0088h: maddr9ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0089h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 008ah: maddr9[47] maddr9[46] maddr9[45] maddr9[44] maddr9[43] maddr9[42] maddr9[41] maddr9[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 008bh: maddr9[39] maddr9[38] maddr9[37] maddr9[36] maddr9[35] maddr9[34] maddr9[33] maddr9[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 9 enable (maddr9ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 9 (maddr9[47:32]) - highest two bytes of mac filter address 9. register name: su.addr9l register description: mac filter address 9 low register address: 008ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 008ch: maddr9[31] maddr9[30] maddr9[29] maddr9[28] maddr9[27] maddr9[26] maddr9[25] maddr9[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 008dh: maddr9[23] maddr9[22] maddr9[21] maddr9[20] maddr9[19] maddr9[18] maddr9[17] maddr9[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 008eh: maddr9[15] maddr9[14] maddr9[13] maddr9[12] maddr9[11] maddr9[10] maddr9[9] maddr9[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 008fh: maddr9[7] maddr9[6] maddr9[5] maddr9[4] maddr9[3] maddr9[2] maddr9[1] maddr9[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 9 (maddr9[31:0]) - lowest four bytes of mac filter address 9. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 293 of 375 register name: su.addr10h register description: mac filter address 10 high register address: 0090h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0090h: maddr10ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0091h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0092h: maddr10[47] maddr10[ 46] maddr10[45] ma ddr10[44] maddr10[43] maddr10[42] maddr 10[41] maddr10[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0093h: maddr10[39] maddr10[ 38] maddr10[37] ma ddr10[36] maddr10[35] maddr10[34] maddr 10[33] maddr10[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 10 enable (maddr10ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 10 (maddr10[47:32]) - highest two bytes of mac filter address 10. register name: su.addr10l register description: mac filter address 10 low register address: 0094h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0094h: maddr10[31] maddr10[ 30] maddr10[29] ma ddr10[28] maddr10[27] maddr10[26] maddr 10[25] maddr10[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0095h: maddr10[23] maddr10[ 22] maddr10[21] ma ddr10[20] maddr10[19] maddr10[18] maddr 10[17] maddr10[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0096h: maddr10[15] maddr10[ 14] maddr10[13] ma ddr10[12] maddr10[11] maddr10[10] maddr 10[9] maddr10[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0097h: maddr10[7] maddr10[ 6] maddr10[5] ma ddr10[4] maddr10[3] maddr10[2] maddr 10[1] maddr10[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 10 (maddr10[31:0]) - lowest four bytes of mac filter address 10. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 294 of 375 register name: su.addr11h register description: mac filter address 11 high register address: 0098h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0098h: maddr11ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0099h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 009ah: maddr11[47] maddr11[ 46] maddr11[45] ma ddr11[44] maddr11[43] maddr11[42] maddr 11[41] maddr11[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 009bh: maddr11[39] maddr11[ 38] maddr11[37] ma ddr11[36] maddr11[35] maddr11[34] maddr 11[33] maddr11[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 11 enable (maddr11ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 11 (maddr11[47:32]) - highest two bytes of mac filter address 11. register name: su.addr11l register description: mac filter address 11 low register address: 009ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 009ch: maddr11[31] maddr11[ 30] maddr11[29] ma ddr11[28] maddr11[27] maddr11[26] maddr 11[25] maddr11[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 009dh: maddr11[23] maddr11[ 22] maddr11[21] ma ddr11[20] maddr11[19] maddr11[18] maddr 11[17] maddr11[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 009eh: maddr11[15] maddr11[ 14] maddr11[13] ma ddr11[12] maddr11[11] maddr11[10] maddr 11[9] maddr11[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 009fh: maddr11[7] maddr11[ 6] maddr11[5] ma ddr11[4] maddr11[3] maddr11[2] maddr 11[1] maddr11[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 11 (maddr11[31:0]) - lowest four bytes of mac filter address 11. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 295 of 375 register name: su.addr12h register description: mac filter address 12 high register address: 00a0h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00a0h: maddr12ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00a1h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00a2h: maddr12[47] maddr12[ 46] maddr12[45] ma ddr12[44] maddr12[43] maddr12[42] maddr 12[41] maddr12[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00a3h: maddr12[39] maddr12[ 38] maddr12[37] ma ddr12[36] maddr12[35] maddr12[34] maddr 12[33] maddr12[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 12 enable (maddr12ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 12 (maddr12[47:32]) - highest two bytes of mac filter address 12. register name: su.addr12l register description: mac filter address 12 low register address: 00a4h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00a4h: maddr12[31] maddr12[ 30] maddr12[29] ma ddr12[28] maddr12[27] maddr12[26] maddr 12[25] maddr12[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00a5h: maddr12[23] maddr12[ 22] maddr12[21] ma ddr12[20] maddr12[19] maddr12[18] maddr 12[17] maddr12[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00a6h: maddr12[15] maddr12[ 14] maddr12[13] ma ddr12[12] maddr12[11] maddr12[10] maddr 12[9] maddr12[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00a7h: maddr12[7] maddr12[ 6] maddr12[5] ma ddr12[4] maddr12[3] maddr12[2] maddr 12[1] maddr12[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 12 (maddr12[31:0]) - lowest four bytes of mac filter address 12. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 296 of 375 register name: su.addr13h register description: mac filter address 13 high register address: 00a8h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00a8h: maddr13ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00a9h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00aah: maddr13[47] maddr13[ 46] maddr13[45] ma ddr13[44] maddr13[43] maddr13[42] maddr 13[41] maddr13[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00abh: maddr13[39] maddr13[ 38] maddr13[37] ma ddr13[36] maddr13[35] maddr13[34] maddr 13[33] maddr13[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 13 enable (maddr13ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 13 (maddr13[47:32]) - highest two bytes of mac filter address 13. register name: su.addr13l register description: mac filter address 13 low register address: 00ach (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00ach: maddr13[31] maddr13[ 30] maddr13[29] ma ddr13[28] maddr13[27] maddr13[26] maddr 13[25] maddr13[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00adh: maddr13[23] maddr13[ 22] maddr13[21] ma ddr13[20] maddr13[19] maddr13[18] maddr 13[17] maddr13[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00aeh: maddr13[15] maddr13[ 14] maddr13[13] ma ddr13[12] maddr13[11] maddr13[10] maddr 13[9] maddr13[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00afh: maddr13[7] maddr13[ 6] maddr13[5] ma ddr13[4] maddr13[3] maddr13[2] maddr 13[1] maddr13[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 13 (maddr13[31:0]) - lowest four bytes of mac filter address 13. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 297 of 375 register name: su.addr14h register description: mac filter address 14 high register address: 00b0h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00b0h: maddr14ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00b1h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00b2h: maddr14[47] maddr14[ 46] maddr14[45] ma ddr14[44] maddr14[43] maddr14[42] maddr 14[41] maddr14[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00b3h: maddr14[39] maddr14[ 38] maddr14[37] ma ddr14[36] maddr14[35] maddr14[34] maddr 14[33] maddr14[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 14 enable (maddr14ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 14 (maddr14[47:32]) - highest two bytes of mac filter address 14. register name: su.addr14l register description: mac filter address 14 low register address: 00b4h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00b4h: maddr14[31] maddr14[ 30] maddr14[29] ma ddr14[28] maddr14[27] maddr14[26] maddr 14[25] maddr14[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00b5h: maddr14[23] maddr14[ 22] maddr14[21] ma ddr14[20] maddr14[19] maddr14[18] maddr 14[17] maddr14[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00b6h: maddr14[15] maddr14[ 14] maddr14[13] ma ddr14[12] maddr14[11] maddr14[10] maddr 14[9] maddr14[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00b7h: maddr14[7] maddr14[ 6] maddr14[5] ma ddr14[4] maddr14[3] maddr14[2] maddr 14[1] maddr14[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 14 (maddr14[31:0]) - lowest four bytes of mac filter address 14. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 298 of 375 register name: su.addr15h register description: mac filter address 15 high register address: 00b8h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00b8h: maddr15ae reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00b9h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00bah: maddr15[47] maddr15[ 46] maddr15[45] ma ddr15[44] maddr15[43] maddr15[42] maddr 15[41] maddr15[40] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00bbh: maddr15[39] maddr15[ 38] maddr15[37] ma ddr15[36] maddr15[35] maddr15[34] maddr 15[33] maddr15[32] default 0 0 0 0 0 0 0 0 bit 31: mac address filter 15 enable (maddr15ae) 0 = address value not used for filtering. 1 = address used for ?p erfect? filtering. bits 0-15: mac address filter 15 (maddr15[47:32]) - highest two bytes of mac filter address 15. register name: su.addr15l register description: mac filter address 15 low register address: 00bch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00b5h: maddr15[31] maddr15[ 30] maddr15[29] ma ddr15[28] maddr15[27] maddr15[26] maddr 15[25] maddr15[24] default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00b6h: maddr15[23] maddr15[ 22] maddr15[21] ma ddr15[20] maddr15[19] maddr15[18] maddr 15[17] maddr15[16] default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00b7h: maddr15[15] maddr15[ 14] maddr15[13] ma ddr15[12] maddr15[11] maddr15[10] maddr 15[9] maddr15[8] default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00b8h: maddr15[7] maddr15[ 6] maddr15[5] ma ddr15[4] maddr15[3] maddr15[2] maddr 15[1] maddr15[0] default 0 0 0 0 0 0 0 0 bits 0-31: mac address filter 15 (maddr15[31:0]) - lowest four bytes of mac filter address 15. see section 8.19.3 for more details on frame-filtering configuration.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 299 of 375 register name: su.pcscr register description: mac physical coding sublayer (pcs) control register register address: 00c0h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00c0h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00c1h: reserved reserved reserved reserved reserved reserved reserved ecd default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00c2h: reserved ele ane reserved reserved reserved ran reserved default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00c3h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 this register configures and initiates auto-negotiation of the external phy device. it also enables phy loopback. bit 16: enable comma detect (ecd) - when set to 1, the mac is enabled for comma detection and word resynchronization. bit 14: external loopback enable (ele) - when set to 1, causes the external phy to loopback the transmit data to the receiver. bit 13: auto-negotiation enable (ane) - when set to 1, the mac will automatically negotiate the link speed with the remote node. when equal to zero, auto-negotiation is disabled. bit 9: restart auto-negotiation (ran) - when set to 1 and ane=1, the mac will initiate auto-negotiation. this bit will clear itself after auto-negotiation is started. should be equal to zero during normal operation.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 300 of 375 register name: su.ansr register description: mac auto-negotiation status register register address: 00c4h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00c4h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00c5h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00c6h: reserved reserved reserved reserved reserved reserved reserved es default 0 0 0 0 0 0 0 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00c7h: reserved reserved anc reserved ans ls reserved reserved default 0 0 0 0 1 0 0 0 bit 8: mac extended status support (es) - this bit is always set to 1, to indicate that the mac supports extended status information. bit 5: auto-negotiation complete (anc) - this bit is set to 1 when auto-negotiation is complete. the bit is equal to zero after auto-negotiation is initiated, and remains zero until completion of auto-negotiation. bit 3: auto-negotiation support (ans) - this bit is always set to 1, to indicate that the mac supports extended auto-negotiation. bit 2: link status (ls) - when set to 1, this bit indicates that the ethernet link is connected. this bit is only updated after a read operation. in order to see t he current status, the bit must be read twice.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 301 of 375 register name: su.lsr register description: mac mii/rmii/gmii status register register address: 00d8h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 00d8h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 00d9h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00dah: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00dbh: reserved reserved rese rved reserved linkup lnkspd[1] lnkspd[0] linkm default 0 0 0 0 0 0 0 0 bit 3: mii/rmii/gmii li nk status (linkup) ? when equal to 1, the link is communicating. when equal to zero, the link is not operational. bits 1-2: link speed (lnkspd[1:0]) ? indicates the current link speed. 00 = 2.5mhz 01 = 25mhz 10 = 125mhz bit 0: link mode (linkm) ? indicates the current link mode. 0 = half-duplex 1 = full-duplex
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 302 of 375 register name: su.mmcctrl register description: mac management counter control register register address: 0100h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0100h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0101h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0102h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0103h: reserved reserved reserved reserved reserved ror csr crst default 0 0 0 0 0 0 0 0 bit 2: reset on read (ror) ? when set to 1, each management counter will reset to zero after a read access of the least-significant byte. when equal to zero , the counters will only be reset by the crst bit. bit 1: counter stop rollover (csr) ? when set to 1, each counter will saturate at the maximum value and not roll over. when equal to zero, each counter can rollove r to zero after the maximum value is exceeded. bit 0: counter reset (crst) ? set to 1 to initiate a reset of all management counters. set to zero for normal operation. 0 = normal operation. 1 = reset all management counters.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 303 of 375 register name: su.mmcrsr register description: mac management counter receive status register register address: 0104h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0104h: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0105h: rxwdog rxvlan rxovfl rxpause rxrange rxlnerr rxufc rx1k_max default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0106h: rx512_1k rx256_511 rx128_255 rx65_127 rx0_64 rxovrsz rxundrsz rxjbbr default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0107h: rxrunt rxalgn rxcrc rxmfc rxgbfc rxgbc rxbc rxfc default 0 0 0 0 0 0 0 0 bits 1-23: receive counter half-full status ? each bit is set to 1 when the corresponding mac mmc counter reaches half of the maximum value. register name: su.mmctsr register description: mac management counter transmit status register register address: 0108h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0108h: reserved reserved reserved reserved reserved reserved reserved txvlan default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0109h: txpause txxcsvdf txfcnt txbcnt txcerr txxcsvcl txltcl txdfrd default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 010ah: txmlticl txsnglcl txufe txbfc txmfc txucast tx1k_max tx512_1k default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 010bh: tx256_511 tx128_255 tx65_127 tx0_64 txgmfc txgbfc txfc txbc default 0 0 0 0 0 0 0 0 bits 1-24: transmit co unter half-full status ? each bit is set to 1 when the corresponding mac mmc counter reaches half of the maximum value.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 304 of 375 register name: su.mmcrim register description: mac management counter receive interrupt mask register address: 010ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 010ch: reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 010dh: rxwdog rxvlan rxovfl rxpause rxrange rxlnerr rxucast rx1k_max default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 010eh: rx512_1k rx256_511 rx128_255 rx65_127 rx0_64 rxovrsz rxundrsz rxjbbr default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 010fh: rxrunt rxalgn rxcrc rxmfc rxgbfc rxgbc rxbc rxfc default 0 0 0 0 0 0 0 0 bits 1-23: receive counter half-full interrupt mask 0 = the corresponding bit in su.mmcrsr can generate an interrupt. 1 = the corresponding bit in su.mmcrsr is masked, and will not generate an interrupt. register name: su.mmctim register description: mac management counter transmit interrupt mask register address: 0110h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0110h: reserved reserved reserved reserved reserved reserved reserved txvlan default 0 0 0 0 0 0 0 0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0111h: txpause txxcsvdf txfcnt txbcnt txcerr txxcsvcl txltcl txdfrd default 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0112h: txmlticl txsnglcl txufe txbfc txmfc txucast tx1k_max tx512_1k default 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0113h: tx256_511 tx128_255 tx65_127 tx0_64 txgmfc txgbfc txfc txbc default 0 0 0 0 0 0 0 0 bits 1-24: transmit counte r half-full interrupt mask 0 = the corresponding bit in su.mmctsr can generate an interrupt. 1 = the corresponding bit in su.mmctsr is masked, and will not generate an interrupt.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 305 of 375 register name: su.txbc register description: mac mmc transmit byte counter register address: 0114h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0114h: txbc[31] txbc[30] txbc[29] txbc[28] txbc[27] txbc[26] txbc[25] txbc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0115h: txbc[23] txbc[22] txbc[21] txbc[20] txbc[19] txbc[18] txbc[17] txbc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0116h: txbc[15] txbc[14] txbc[13] txbc[12] txbc[11] txbc[10] txbc[9] txbc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0117h: txbc[7] txbc[6] txbc[5 ] txbc[4] txbc[3] txbc [2] txbc[1] txbc[0] bits 1-31: transmit byte counter (txbc[31:0]) ? contains the number of bytes (oct ets) transmitted, exclusive of both preamble and retried bytes, in both good and bad frames. register name: su.txfc register description: mac mmc transmit frame counter register address: 0118h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0118h: txfc[31] txfc[30] txfc[29] txfc[28] txfc[27] txfc [26] txfc[25] txfc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0119h: txfc[23] txfc[22] txfc[21] txfc[20] txfc[19] txfc [18] txfc[17] txfc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 011ah: txfc[15] txfc[14] txfc[ 13] txfc[12] txfc[11] txfc[10] txfc[9] txfc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 011bh: txfc[7] txfc[6] txfc[5] txfc[4] txfc[3] txfc[2] txfc[1] txfc[0] bits 1-31: transmit frame counter (txfc[31:0]) ? contains the number of frames transmitted, including both good and bad frames.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 306 of 375 register name: su.txgbfc register description: mac mmc transmit good broadcast frames counter register address: 011ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 011ch: txgbfc[31] txgbfc[30] txgbfc[ 29] txgbfc[28] txgbfc[27] txgbfc [26] txgbfc[25] txgbfc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 011dh: txgbfc[23] txgbfc[22] txgbfc[ 21] txgbfc[20] txgbfc[19] txgbfc [18] txgbfc[17] txgbfc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 011eh: txgbfc[15] txgbfc[14] txgbfc [13] txgbfc[12] txgbfc[11] txgb fc[10] txgbfc[9] txgbfc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 011fh: txgbfc[7] txgbfc[6] txgbfc[5] txgbfc[4] txgbfc[3] txgbfc[2] txgbfc[1] txgbfc[0] bits 1-31: transmit good broadcast frames counter (txgbfc[31:0]) ? contains the number of good broadcast frames transmitted, exclusive of both prea mble and retried bytes. does not contain bad frames. register name: su.txgmfc register description: mac mmc transmit good multicast frames counter register address: 0120h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0120h: txgmfc[31] txgmfc[30] txgmfc[29] txgmfc[28] tx gmfc[27] txgmfc[26] tx gmfc[25] txgmfc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0121h: txgmfc[23] txgmfc[22] txgmfc[21] txgmfc[20] tx gmfc[19] txgmfc[18] tx gmfc[17] txgmfc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0122h: txgmfc[15] txgmfc[14] txgmfc[13] txgmfc[12] txgmfc[11] txgmfc[10] txgmfc[9] txgmfc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0123h: txgmfc[7] txgmfc[6] txgmfc[5] txgmfc[4] txgmfc[3] txgmfc[2] txgmfc[1] txgmfc[0] bits 1-31: transmit good multicast frames counter (txgmfc[31:0]) ? contains the number of good multicast frames transmitted.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 307 of 375 register name: su.tx0_64 register description: mac mmc transmit 0-64 byte frame counter register address: 0124h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0124h: tx0_64[31] tx0_64[30] tx0_64[29] tx0_64[28] tx0_64[27] tx0_64[26] tx0_64[25] tx0_64[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0125h: tx0_64[23] tx0_64[22] tx0_64[21] tx0_64[20] tx0_64[19] tx0_64[18] tx0_64[17] tx0_64[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0126h: tx0_64[15] tx0_64[14] tx0_64[13] tx0_64[12] tx0_64[11] tx0_64[10] tx0_64[9] tx0_64[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0127h: tx0_64[7] tx0_64[6] tx0_64[5] tx0_64[4] tx0_64[3] tx0_64[2] tx0_64[1] tx0_64[0] bits 1-31: transmit 0-64 byte frames counter (tx0_64[31:0]) ? contains the number of frames transmitted with sizes of 64 bytes or less. includes both good and bad frames. register name: su.tx65_127 register description: mac mmc transmit 65-127 byte frames counter register address: 0128h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0128h: tx65_127[31] tx65_127[30] tx65_127[29] tx65_127[28] tx65_127[27] tx65_127[26] tx65_127[25] tx65_127[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0129h: tx65_127[23] tx65_127[22] tx65_127[21] tx65_127[20] tx65_127[19] tx65_127[18] tx65_127[17] tx65_127[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 012ah: tx65_127[15] tx65_127[14] tx65_127[13] tx65_127[12] tx65_127[11] tx65_127[10] tx65_127[9] tx65_127[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 012bh: tx65_127[7] tx65_127[6] tx65_127[5] tx65_127[4] tx65_127[3] tx65_127[2] tx65_127[1] tx65_127[0] bits 1-31: transmit 65-127 byte frames counter (tx65_127[31:0]) ? contains the number of frames transmitted with sizes of 65 to 127 bytes. includes both good and bad frames.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 308 of 375 register name: su.tx128_255 register description: mac mmc transmit 128-255 byte frame counter register address: 012ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 012ch: tx128_255[31] tx128_255[30] tx128_255[29] tx128_255[28] tx128_255[27] tx128_255[26] tx128_255[25] tx128_255[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 012dh: tx128_255[23] tx128_255[22] tx128_255[21] tx128_255[20] tx128_255[19] tx128_255[18] tx128_255[17] tx128_255[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 012eh: tx128_255[15] tx128_255[14] tx128_255[13] tx128_255[12] tx128_255[11] tx128_255[10] tx128_255[9] tx128_255[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 012fh: tx128_255[7] tx128_255[6] tx128_255[5] tx128_255[4] tx128_255[3] tx128_255[2] tx128_255[1] tx128_255[0] bits 1-31: transmit 128-255 byte frames counter (tx128_255[31:0]) ? contains the number of frames transmitted with sizes of 128 to 255 bytes. includes both good and bad frames. register name: su.tx256_511 register description: mac mmc transmit 256-511 byte frames counter register address: 0130h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0130h: tx256_511[31] tx256_511[30] tx256_511[29] tx256_511[28] tx256_511[27] tx256_511[26] tx256_511[25] tx256_511[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0131h: tx256_511[23] tx256_511[22] tx256_511[21] tx256_511[20] tx256_511[19] tx256_511[18] tx256_511[17] tx256_511[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0132h: tx256_511[15] tx256_511[14] tx256_511[13] tx256_511[12] tx256_511[11] tx256_511[10] tx256_511[9] tx256_511[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0133h: tx256_511[7] tx256_511[6] tx256_511[5] tx256_511[4] tx256_511[3] tx256_511[2] tx256_511[1] tx256_511[0] bits 1-31: transmit 256-511 byte frames counter (tx256_511[31:0]) ? contains the number of frames transmitted with sizes of 256 to 511 bytes. includes both good and bad frames.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 309 of 375 register name: su.tx512_1k register description: mac mmc transmit 512-1023 byte frame counter register address: 0134h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0134h: tx512_1k[31] tx512_1k[30] tx512_1k[29] tx512_1k[28] tx512_1k[27] tx512_1k[26] tx512_1k[25] tx512_1k[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0135h: tx512_1k[23] tx512_1k[22] tx512_1k[21] tx512_1k[20] tx512_1k[19] tx512_1k[18] tx512_1k[17] tx512_1k[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0136h: tx512_1k[15] tx512_1k[14] tx512_1k[13] tx512_1k[12] tx512_1k[11] tx512_1k[10] tx512_1k[9] tx512_1k[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0137h: tx512_1k[7] tx512_1k[6] tx512_1k[5] tx512_1k[4] tx512_1k[3] tx512_1k[2] tx512_1k[1] tx512_1k[0] bits 1-31: transmit 512-1023 byte frames counter (tx512_1k[31:0]) ? contains the number of frames transmitted with sizes of 512 to 1023 bytes. includes both good and bad frames. register name: su.tx1k_max register description: mac mmc transmit 1024-max byte frames counter register address: 0138h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0138h: tx1k_max[31] tx1k_max[30] tx1k_max[29] tx1k_max[28] tx1k_max[27] tx1k_max[26] tx1k_max[25] tx1k_max[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0139h: tx1k_max[23] tx1k_max[22] tx1k_max[21] tx1k_max[20] tx1k_max[19] tx1k_max[18] tx1k_max[17] tx1k_max[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 013ah: tx1k_max[15] tx1k_max[14] tx1k_max[13] tx1k_max[12] tx1k_max[11] tx1k_max[10] tx1k_max[9] tx1k_max[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 013bh: tx1k_max[7] tx1k_max[6] tx1k_max[5] tx1k_max[4] tx1k_max[3] tx1k_max[2] tx1k_max[1] tx1k_max[0] bits 1-31: transmit 1024-max byte frames counter (tx1k_max[31:0]) ? contains the number of frames transmitted with sizes of 1024 to the maximum allo wed bytes. includes both good and bad frames.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 310 of 375 register name: su.txucast register description: mac mmc transmit unicast frame counter register address: 013ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 013ch: txucast[31] txucast[30] txucast[29] txucast[28] txucast[27] txucast[26] txucast[25] txucast[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 013dh: txucast[23] txucast[22] txucast[21] txucast[20] txucast[19] txucast[18] txucast[17] txucast[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 013eh: txucast[15] txucast[14] txucast[13] txucast[12] txucast[11] txucast[10] txucast[9] txucast[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 013fh: txucast[7] txucast[6] txucast[5] txucast[4] txucast[3] txucast[2] txucast[1] txucast[0] bits 1-31: transmit unicast frames counter (txucast[31:0]) ? contains the number of frames transmitted with a unicast address. includes both good and bad frames. register name: su.txmfc register description: mac mmc transmit multicast frames counter register address: 0140h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0140h: txmfc[31] txmfc[30] txmfc[29] txmfc[28] txmfc[27] txmfc[26] txmfc[25] txmfc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0141h: txmfc[23] txmfc[22] txmfc[21] txmfc[20] txmfc[19] txmfc[18] txmfc[17] txmfc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0142h: txmfc[15] txmfc[14] txmfc[13] txmfc[12] txmfc[11] txmfc[10] txmfc[9] txmfc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0143h: txmfc[7] txmfc[6] txmfc[5] txmfc[4] txmfc[3] txmfc[2] txmfc[1] txmfc[0] bits 1-31: transmit multicast frames counter (txmfc[31:0]) ? contains the number of frames transmitted with a multicast address. includes both good and bad frames.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 311 of 375 register name: su.txbfc register description: mac mmc transmit broadcast frame counter register address: 0144h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0144h: txbfc[31] txbfc[30] txbfc[29] txbfc[28] txbfc[27] txbfc[26] txbfc[25] txbfc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0145h: txbfc[23] txbfc[22] txbfc[21] txbfc[20] txbfc[19] txbfc[18] txbfc[17] txbfc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0146h: txbfc[15] txbfc[14] txbfc[13] txbfc[12] txbfc[11] txbfc[10] txbfc[9] txbfc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0147h: txbfc[7] txbfc[6] txbfc[5] txbfc[4] txbfc[3] txbfc[2] txbfc[1] txbfc[0] bits 1-31: transmit broadcast frames counter (txbfc[31:0]) ? contains the number of frames transmitted with a broadcast address. includes both good and bad frames. register name: su.txufe register description: mac mmc transmit underflow frames counter register address: 0148h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0148h: txufe[31] txufe[30] txufe[29] txufe[28] txufe[27] txufe[26] txufe[25] txufe[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0149h: txufe[23] txufe[22] txufe[21] txufe[20] txufe[19] txufe[18] txufe[17] txufe[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 014ah: txufe[15] txufe[14] txufe[13] txufe[12] txufe[11] txufe[10] txufe[9] txufe[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 014bh: txufe[7] txufe[6] txufe[5] txufe[4] txufe[3] txufe[2] txufe[1] txufe[0] bits 1-31: transmit underflow frames counter (txufe[31:0]) ? contains the number of frames aborted due to underflow errors.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 312 of 375 register name: su.txsnglcl register description: mac mmc transmit single collision frame counter register address: 014ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 014ch: txsnglcl[31] txsnglcl[30] txsnglcl[29] txsnglcl[28] txsnglcl[27] txsnglcl[26] txsnglcl[25] txsnglcl[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 014dh: txsnglcl[23] txsnglcl[22] txsnglcl[21] txsnglcl[20] txsnglcl[19] txsnglcl[18] txsnglcl[17] txsnglcl[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 014eh: txsnglcl[15] txsnglcl[14] txsnglcl[13] txsnglcl[12] txsnglcl[11] txsnglcl[10] txsnglcl[9] txsnglcl[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 014fh: txsnglcl[7] txsnglcl[6] txsnglcl[5] txsnglcl[4] txsnglcl[3] txsnglcl[2] txsnglcl[1] txsnglcl[0] bits 1-31: transmit single collisi on frames counter (txsnglcl[31:0]) ? contains the number of frames successfully transmitted after a single co llision. applicable in half-duplex mode only. register name: su.txmlticl register description: mac mmc transmit multiple collision frames counter register address: 0150h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0150h: txmlticl[31] txmlticl[30] txmlticl[29] txmlticl[28] txmlticl[27] txmlticl[26] txmlticl[25] txmlticl[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0151h: txmlticl[23] txmlticl[22] txmlticl[21] txmlticl[20] txmlticl[19] txmlticl[18] txmlticl[17] txmlticl[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0152h: txmlticl[15] txmlticl[14] txmlticl[13] txmlticl[12] txmlticl[11] txmlticl[10] txmlticl[9] txmlticl[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0153h: txmlticl[7] txmlticl[6] txmlticl[5] txmlticl[4] txmlticl[3] txmlticl[2] txmlticl[1] txmlticl[0] bits 1-31: transmit multiple collis ion frames counter (txmlticl[31:0]) ? contains the number of frames successfully transmitted after multiple co llisions. applicable in half-duplex mode only.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 313 of 375 register name: su.txdfrd register description: mac mmc transmit deferred frame counter register address: 0154h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0154h: txdfrd[31] txdfrd[30] txdfrd[29] txdfrd[28] txdfrd[27] txdfrd[26] txdfrd[25] txdfrd[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0155h: txdfrd[23] txdfrd[22] txdfrd[21] txdfrd[20] txdfrd[19] txdfrd[18] txdfrd[17] txdfrd[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0156h: txdfrd[15] txdfrd[14] txdfrd[13] txdfrd[12] txdfrd[11] txdfrd[10] txdfrd[9] txdfrd[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0157h: txdfrd[7] txdfrd[6] txdfrd[5] txdfrd[4] txdfrd[3] txdfrd[2] txdfrd[1] txdfrd[0] bits 1-31: transmit deferred frames counter (txdfrd[31:0]) ? contains the number of frames successfully transmitted after deferral. applic able in half-duplex mode only. register name: su.txltcl register description: mac mmc transmit late collision frames counter register address: 0158h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0158h: txltcl[31] txltcl[30] txltcl[29] txltcl[28] txltcl[27] txltcl[26] txltcl[25] txltcl[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0159h: txltcl[23] txltcl[22] txltcl[21] txltcl[20] txltcl[19] txltcl[18] txltcl[17] txltcl[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 015ah: txltcl[15] txltcl[14] txltcl[13] txltcl[12] txltcl[11] txltcl[10] txltcl[9] txltcl[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 015bh: txltcl[7] txltcl[6] txltcl[5] txltcl[4] txltcl[3] txltcl[2] txltcl[1] txltcl[0] bits 1-31: transmit late collis ion frames counter (txltcl[31:0]) ? contains the number of frames aborted due to late collisions. applicable in half-duplex mode only.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 314 of 375 register name: su.txxcsvcl register description: mac mmc transmit excessive collision counter register address: 015ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 015ch: txxcsvcl[31] txxcsvcl[30] txxcsvcl[29] txxcsvcl[28] txxcsvcl[27] txxcsvcl[26] txxcsvcl[25] txxcsvcl[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 015dh: txxcsvcl[23] txxcsvcl[22] txxcsvcl[21] txxcsvcl[20] txxcsvcl[19] txxcsvcl[18] txxcsvcl[17] txxcsvcl[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 015eh: txxcsvcl[15] txxcsvcl[14] txxcsvcl[13] txxcsvcl[12] txxcsvcl[11] txxcsvcl[10] txxcsvcl[9] txxcsvcl[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 015fh: txxcsvcl[7] txxcsvcl[6] txxcsvcl[ 5] txxcsvcl[4] txxcsvcl[3] txxc svcl[2] txxcsvcl[1] txxcsvcl[0] bits 1-31: transmit excessive collision c ounter (txxcsvcl[31:0]) ? contains the number of frames aborted due to excessive collisions. applicable in half-duplex mode only. register name: su.txcrerr register description: mac mmc transmit carrier error counter register address: 0160h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0160h: txcrerr[31] txcrerr[30] txcrerr[29 ] txcrerr[28] txcrerr[27] txcre rr[26] txcrerr[25] txcrerr[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0161h: txcrerr[23] txcrerr[22] txcrerr[21 ] txcrerr[20] txcrerr[19] txcre rr[18] txcrerr[17] txcrerr[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0162h: txcrerr[15] txcrerr[14] txcrerr[13 ] txcrerr[12] txcrerr[11] txcrerr[10] txcrerr[9] txcrerr[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0163h: txcrerr[7] txcrerr[6] txcrerr[5] txcrerr[4] txcrerr[3] txcrerr[2] txcrerr[1] txcrerr[0] bits 1-31: transmit carrier error counter (txcrerr[31:0]) ? contains the number of frames aborted due to carrier error (no carrier or loss of carrier).
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 315 of 375 register name: su.txgbc register description: mac mmc transmit good byte counter register address: 0164h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0164h: txgbc[31] txgbc[30] txgbc[29] txgbc[28] txgbc[27] txgbc[26] txgbc[25] txgbc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0165h: txgbc[23] txgbc[22] txgbc[21] txgbc[20] txgbc[19] txgbc[18] txgbc[17] txgbc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0166h: txgbc[15] txgbc[14] txgbc[13] txgbc[12] txgbc[11] txgbc[10] txgbc[9] txgbc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0167h: txgbc[7] txgbc[6] txgbc[5] txgbc[4] txgbc[3] txgbc[2] txgbc[1] txgbc[0] bits 1-31: transmit good byte counter (txgbc[31:0]) ? contains the number of transmitted bytes in good frames, exclusive of preamble bytes. register name: su.txgfc register description: mac mmc transmit good frame counter register address: 0168h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0168h: txgfc[31] txgfc[30] txgfc[29] txgfc[28] txgfc[27] txgfc[26] txgfc[25] txgfc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0169h: txgfc[23] txgfc[22] txgfc[21] txgfc[20] txgfc[19] txgfc[18] txgfc[17] txgfc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 016ah: txgfc[15] txgfc[14] txgfc[13] txgfc[12] txgfc[11] txgfc[10] txgfc[9] txgfc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 016bh: txgfc[7] txgfc[6] txgfc[5] txgfc[4] txgfc[3] txgfc[2] txgfc[1] txgfc[0] bits 1-31: transmit good frame counter (txgfc[31:0]) ? contains the number of good frames transmitted.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 316 of 375 register name: su.txxcsvdf register description: mac mmc transmit excessive deferral counter register address: 016ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 016ch: txxcsvdf[31] txxcsvdf[30] txxcsvdf[29] txxcsvdf[28] txxcsvdf[27] txxcsvdf[26] txxcsvdf[25] txxcsvdf[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 016dh: txxcsvdf[23] txxcsvdf[22] txxcsvdf[21] txxcsvdf[20] txxcsvdf[19] txxcsvdf[18] txxcsvdf[17] txxcsvdf[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 016eh: txxcsvdf[15] txxcsvdf[14] txxcsvdf[13] txxcsvdf[12] txxcsvdf[11] txxcsvdf[10] txxcsvdf[9] txxcsvdf[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 016fh: txxcsvdf[7] txxcsvdf[6] txxcsvdf[5] txxcsvdf[4] txxcsvdf[3] txxcsvdf[2] txxcsvdf[1] txxcsvdf[0] bits 1-31: transmit excessive deferral counter (txxcsvdf[31:0]) ? contains the number of frames aborted due to excessive deferral. applic able in half-duplex mode only. register name: su.txpause register description: mac mmc transmit pause frame counter register address: 0170h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0170h: txpause[31] txpause[30] txpause[29] txpause[28] txpause[27] txpause[26] txpause[25] txpause[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0171h: txpause[23] txpause[22] txpause[21] txpause[20] txpause[19] txpause[18] txpause[17] txpause[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0172h: txpause[15] txpause[14] txpause[13] txpause[12] txpause[11] txpause[10] txpause[9] txpause[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0173h: txpause[7] txpause[6] txpause[5] txpause[4] txpause[3] txpause[2] txpause[1] txpause[0] bits 1-31: transmit pause frame counter (txpause[31:0]) ? contains the number of good pause frames transmitted.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 317 of 375 register name: su.txvlanf register description: mac mmc transmit vlan frame counter register address: 0174h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0174h: txvlanf[31] txvlanf[30] txvlanf[ 29] txvlanf[28] txvlanf[27] txvl anf[26] txvlanf[25] txvlanf[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0175h: txvlanf[23] txvlanf[22] txvlanf[ 21] txvlanf[20] txvlanf[19] txvl anf[18] txvlanf[17] txvlanf[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0176h: txvlanf[15] txvlanf[14] txvlanf[ 13] txvlanf[12] txvlanf[11] txvl anf[10] txvlanf[9] txvlanf[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0177h: txvlanf[7] txvlanf[6] txvlanf[ 5] txvlanf[4] txvlanf[3] txvl anf[2] txvlanf[1] txvlanf[0] bits 1-31: transmit vlan frame counter (txvlanf[31:0]) ? contains the number of good vlan frames transmitted. register name: su.rxfc register description: mac mmc receive frame counter register address: 0180h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0180h: rxfc[31] rxfc[30] rxfc[29] rxfc[28] rxfc[27] rxfc[26] rxfc[25] rxfc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0181h: rxfc[23] rxfc[22] rxfc[21] rxfc[20] rxfc[19] rxfc[18] rxfc[17] rxfc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0182h: rxfc[15] rxfc[14] rxfc[13] rxfc[12] rxfc[11] rxfc[10] rxfc[9] rxfc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0183h: rxfc[7] rxfc[6] rxfc[5] rxfc[4] rxfc[3] rxfc[2] rxfc[1] rxfc[0] bits 1-31: receive fram e counter (rxfc[31:0]) ? contains the number of frames received, both good and bad frames included.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 318 of 375 register name: su.rxbc register description: mac mmc receive byte counter register address: 0184h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0184h: rxbc[31] rxbc[30] rxbc[29] rxbc[28] rxbc[27] rxbc [26] rxbc[25] rxbc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0185h: rxbc[23] rxbc[22] rxbc[21] rxbc[20] rxbc[19] rxbc [18] rxbc[17] rxbc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0186h: rxbc[15] rxbc[14] rxbc[13] rxbc[12] rxbc[11] rxbc[10] rxbc[9] rxbc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0187h: rxbc[7] rxbc[6] rxbc[5] rxbc[4] rxbc[3] rxbc[2] rxbc[1] rxbc[0] bits 1-31: receive byte counter (rxbc[31:0]) ? contains the number of good and bad bytes received, exclusive of preamble bytes. register name: su.rxgbc register description: mac mmc receive good byte counter register address: 0188h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0188h: rxgbc[31] rxgbc[30] rxgbc[29 ] rxgbc[28] rxgbc[27] rxgbc[26] rxgbc[25] rxgbc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0189h: rxgbc[23] rxgbc[22] rxgbc[21 ] rxgbc[20] rxgbc[19] rxgbc[18] rxgbc[17] rxgbc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 018ah: rxgbc[15] rxgbc[14] rxgbc[13 ] rxgbc[12] rxgbc[11] rxgbc[10] rxgbc[9] rxgbc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 018bh: rxgbc[7] rxgbc[6] rxgbc[5] rxgbc[4] rxgbc[3] rxgbc[2] rxgbc[1] rxgbc[0] bits 1-31: receive good byte counter (rxgbc[31:0]) ? contains the number of bytes received in good frames, exclusive of preamble bytes.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 319 of 375 register name: su.rxgbfc register description: mac mmc receive good broadcast frame counter register address: 018ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 018ch: rxgbfc[31] rxgbfc[30] rxgbfc[ 29] rxgbfc[28] rxgbfc[27] rxgb fc[26] rxgbfc[ 25] rxgbfc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 018dh: rxgbfc[23] rxgbfc[22] rxgbfc[ 21] rxgbfc[20] rxgbfc[19] rxgb fc[18] rxgbfc[ 17] rxgbfc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 018eh: rxgbfc[15] rxgbfc[14] rxgbfc[ 13] rxgbfc[12] rxgb fc[11] rxgbfc[10] rxgbfc[9] rxgbfc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 018fh: rxgbfc[7] rxgbfc[6] rxgbfc[5] rxgbfc[4] rxgbfc[3] rxgbfc[2] rxgbfc[1] rxgbfc[0] bits 1-31: receive good broadcast frame counter (rxgbfc[31:0]) ? contains the number of good broadcast frames received. register name: su.rxmfc register description: mac mmc receive multicast frame counter register address: 0190h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0190h: rxmfc[31] rxmfc[30] rxmfc[29] rxmfc[28] rxmfc[27] rxmfc[26] rxmfc[25] rxmfc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0191h: rxmfc[23] rxmfc[22] rxmfc[21] rxmfc[20] rxmfc[19] rxmfc[18] rxmfc[17] rxmfc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0192h: rxmfc[15] rxmfc[14] rxmfc[13] rxmfc[12] rxmfc[11] rxmfc[10] rxmfc[9] rxmfc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0193h: rxmfc[7] rxmfc[6] rxmfc[5] rxmfc[4] rxmfc[3] rxmfc[2] rxmfc[1] rxmfc[0] bits 1-31: receive good multicas t frame counter (rxmfc[31:0]) ? contains the number of good multicast frames received.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 320 of 375 register name: su.rxcrc register description: mac mmc receive crc error counter register address: 0194h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0194h: rxcrc[31] rxcrc[30] rxcrc[29] rxcrc[28] rxcrc[27] rxcrc[26] rxcrc[25] rxcrc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0195h: rxcrc[23] rxcrc[22] rxcrc[21] rxcrc[20] rxcrc[19] rxcrc[18] rxcrc[17] rxcrc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0196h: rxcrc[15] rxcrc[14] rxcrc[13] rxcrc[12] rxcrc[11] rxcrc[10] rxcrc[9] rxcrc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0197h: rxcrc[7] rxcrc[6] rxcrc[5] rxcrc[4] rxcrc[3] rxcrc[2] rxcrc[1] rxcrc[0] bits 1-31: receive crc error counter (rxcrc[31:0]) ? contains the number of frames received with crc errors. register name: su.rxalgn register description: mac mmc receive alignment error counter register address: 0198h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0198h: rxalgn[31] rxalgn[30] rxalgn[29] rxalgn[28] rxalgn[27] rxalgn[26] rxalgn[25] rxalgn[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0199h: rxalgn[23] rxalgn[22] rxalgn[21] rxalgn[20] rxalgn[19] rxalgn[18] rxalgn[17] rxalgn[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 019ah: rxalgn[15] rxalgn[14] rxalgn[13] rxalgn[12] rxalgn[11] rxalgn[10] rxalgn[9] rxalgn[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 019bh: rxalgn[7] rxalgn[6] rxalgn[5] rxalgn[4] rxalgn[3] rxalgn[2] rxalgn[1] rxalgn[0] bits 1-31: receive alignment error counter (rxalgn[31:0]) ? contains the number of frames received with alignment (dribble) errors.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 321 of 375 register name: su.rxrunt register description: mac mmc receive runt error counter register address: 019ch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 019ch: rxrunt[31] rxrunt[30] rxrunt[29] rxrunt[28] rxrunt[27] rxrunt[26] rxrunt[25] rxrunt[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 019dh: rxrunt[23] rxrunt[22] rxrunt[21] rxrunt[20] rxrunt[19] rxrunt[18] rxrunt[17] rxrunt[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 019eh: rxrunt[15] rxrunt[14] rxrunt[13] rxrunt[12] rxrunt[11] rxrunt[10] rxrunt[9] rxrunt[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 019fh: rxrunt[7] rxrunt[6] rxrunt[5] rxrunt[4] rxrunt[3] rxrunt[2] rxrunt[1] rxrunt[0] bits 1-31: receive runt error counter (rxrunt[31:0]) ? contains the number of runt frames received. register name: su.rxjbbr register description: mac mmc receive jabber error counter register address: 01a0h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01a0h: rxjbbr[31] rxjbbr[30] rxjbbr[2 9] rxjbbr[28] rxjbbr[27] rxj bbr[26] rxjbbr[25] rxjbbr[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01a1h: rxjbbr[23] rxjbbr[22] rxjbbr[2 1] rxjbbr[20] rxjbbr[19] rxj bbr[18] rxjbbr[17] rxjbbr[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01a2h: rxjbbr[15] rxjbbr[14] rxjbbr[1 3] rxjbbr[12] rxjbbr[11] rx jbbr[10] rxjbbr[9] rxjbbr[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01a3h: rxjbbr[7] rxjbbr[6] rxjbbr[5] rxjbbr[4] rxjbbr[3] rxjbbr[2] rxjbbr[1] rxjbbr[0] bits 1-31: receive jabber error counter (rxjbbr[31:0]) ? contains the number of frames received with length greater 1518 (including the crc) and with crc errors.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 322 of 375 register name: su.rxundrsz register description: mac mmc receive undersize frame counter register address: 01a4h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01a4h: rxundrsz[31] rxundrsz[30] rxundrsz[29] rxundrsz[28] rxundrsz[27] rxundrsz[26] rxundrsz[25] rxundrsz[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01a5h: rxundrsz[23] rxundrsz[22] rxundrsz[21] rxundrsz[20] rxundrsz[19] rxundrsz[18] rxundrsz[17] rxundrsz[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01a6h: rxundrsz[15] rxundrsz[14] rxundrsz[13] rxundrsz[12] rxundrsz[11] rxundrsz[10] rxundrsz[9] rxundrsz[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01a7h: rxundrsz[7] rxundrsz[6] rxundrsz[5] rxundrsz[4] rxundrsz[3] rxundrsz[2] rxundrsz[1] rxundrsz[0] bits 1-31: receive undersize frame counter (rxundrsz[31:0]) ? contains the number of frames received with a size less than 64 bytes and a good crc. register name: su.rxovrsz register description: mac mmc receive oversize frame counter register address: 01a8h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01a8h: rxovrsz[31] rxovrsz[30] rxovrsz[29] rxovrsz[28] rxovrsz[27] rxovrsz[26] rxovrsz[25] rxovrsz[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01a9h: rxovrsz[23] rxovrsz[22] rxovrsz[21] rxovrsz[20] rxovrsz[19] rxovrsz[18] rxovrsz[17] rxovrsz[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01aah: rxovrsz[15] rxovrsz[14] rxovrsz[13] rxovrsz[12] rxovrsz[11] rxovrsz[10] rxovrsz[9] rxovrsz[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01abh: rxovrsz[7] rxovrsz[6] rxovrsz[5] rxovrsz[4] rxovrsz[3] rxovrsz[2] rxovrsz[1] rxovrsz[0] bits 1-31: receive oversize frame counter (rxovrsz[31:0]) ? contains the number of frames received with length greater than the maximum size with a valid crc.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 323 of 375 register name: su.rx0_64 register description: mac mmc receive 0-64 byte frame counter register address: 01ach (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01ach: rx0_64[31] rx0_64[30] rx0_64[29] rx0_64[28] rx0_64[27] rx0_64[26] rx0_64[25] rx0_64[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01adh: rx0_64[23] rx0_64[22] rx0_64[21] rx0_64[20] rx0_64[19] rx0_64[18] rx0_64[17] rx0_64[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01aeh: rx0_64[15] rx0_64[14] rx0_64[13] rx0_64[12] rx0_64[11] rx0_64[10] rx0_64[9] rx0_64[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01afh: rx0_64[7] rx0_64[6] rx0_64[5] rx0_64[4] rx0_64[3] rx0_64[2] rx0_64[1] rx0_64[0] bits 1-31: receive 0-64 byte frames counter (rx0_64[31:0]) ? contains the number of frames received with sizes of 64 bytes or less. includes both good and bad frames. register name: su.rx65_127 register description: mac mmc receive 65-127 byte frame counter register address: 01b0h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01b0h: rx65_127[31] rx65_127[30] rx65_127[29] rx65_127[28] rx65_127[27] rx65_127[26] rx65_127[25] rx65_127[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01b1h: rx65_127[23] rx65_127[22] rx65_127[21] rx65_127[20] rx65_127[19] rx65_127[18] rx65_127[17] rx65_127[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01b2h: rx65_127[15] rx65_127[14] rx65_127[13] rx65_127[12] rx65_127[11] rx65_127[10] rx65_127[9] rx65_127[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01b3h: rx65_127[7] rx65_127[6] rx65_127[5] rx65_127[4] rx65_127[3] rx65_1 27[2] rx65_127[1] rx65_127[0] bits 1-31: receive 65-127 byte frames counter (rx65_127[31:0]) ? contains the number of frames received with sizes of 65 to 127 bytes. includes both good and bad frames.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 324 of 375 register name: su.rx128_255 register description: mac mmc receive 128-255 byte frame counter register address: 01b4h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01b4h: rx128_255[31] rx128_255[30] rx128_255[29] rx128_255[28] rx128_255[27] rx128_255[26] rx128_255[25] rx128_255[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01b5h: rx128_255[23] rx128_255[22] rx128_255[21] rx128_255[20] rx128_255[19] rx128_255[18] rx128_255[17] rx128_255[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01b6h: rx128_255[15] rx128_255[14] rx128_255[13] rx128_255[12] rx128_255[11] rx128_255[10] rx128_255[9] rx128_255[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01b7h: rx128_255[7] rx128_255[6] rx128_255[5] rx128_255[4] rx128_255[3] rx128_255[2] rx128_255[1] rx128_255[0] bits 1-31: receive 128-255 byte frames counter (rx128_255[31:0]) ? contains the number of frames received with sizes of 128 to 255 bytes. includes both good and bad frames. register name: su.rx256_511 register description: mac mmc receive 256-511 byte frame counter register address: 01b8h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01b8h: rx256_511[31] rx256_511[30] rx256_511[29] rx256_511[28] rx256_511[27] rx256_511[26] rx256_511[25] rx256_511[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01b9h: rx256_511[23] rx256_511[22] rx256_511[21] rx256_511[20] rx256_511[19] rx256_511[18] rx256_511[17] rx256_511[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01bah: rx256_511[15] rx256_511[14] rx256_511[13] rx256_511[12] rx256_511[11] rx256_511[10] rx256_511[9] rx256_511[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01bbh: rx256_511[7] rx256_511[6] rx256_511[5] rx256_511[4] rx256_511[3] rx256_511[2] rx256_511[1] rx256_511[0] bits 1-31: receive 256-511 byte frames counter (rx256_511[31:0]) ? contains the number of frames received with sizes of 256 to 511 bytes. includes both good and bad frames.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 325 of 375 register name: su.rx512_1k register description: mac mmc receive 512-1023 byte frame counter register address: 01bch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01bch: rx512_1k[31] rx512_1k[30] rx512_1k[29] rx512_1k[28] rx512_1k[27] rx512_1k[26] rx512_1k[25] rx512_1k[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01bdh: rx512_1k[23] rx512_1k[22] rx512_1k[21] rx512_1k[20] rx512_1k[19] rx512_1k[18] rx512_1k[17] rx512_1k[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01beh: rx512_1k[15] rx512_1k[14] rx512_1k[13] rx512_1k[12] rx512_1k[11] rx512_1k[10] rx512_1k[9] rx512_1k[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01bfh: rx512_1k[7] rx512_1k[6] rx512_1k[5] rx512_1k[4] rx512_1k[3] rx512_1k[2] rx512_1k[1] rx512_1k[0] bits 1-31: receive 512-1023 byte frames counter (rx512_1k[31:0]) ? contains the number of frames received with sizes of 512 to 1023 bytes. includes both good and bad frames. register name: su.rx1k_max register description: mac mmc receive 1024-max byte frame counter register address: 01c0h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01c0h: rx1k_max[31] rx1k_max[30] rx1k_max[29] rx1k_max[28] rx1k_max[27] rx1k_max[26] rx1k_max[25] rx1k_max[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01c1h: rx1k_max[23] rx1k_max[22] rx1k_max[21] rx1k_max[20] rx1k_max[19] rx1k_max[18] rx1k_max[17] rx1k_max[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01c2h: rx1k_max[15] rx1k_max[14] rx1k_max[13] rx1k_max[12] rx1k_max[11] rx1k_max[10] rx1k_max[9] rx1k_max[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01c3h: rx1k_max[7] rx1k_max[6] rx1k_max[5] rx1k_max[4] rx1k_max[3] rx1k_max[2] rx1k_max[1] rx1k_max[0] bits 1-31: receive 1024-max byte frames counter (rx1k_max[31:0]) ? contains the number of frames received with sizes of 1024 to the maximu m bytes. includes both good and bad frames.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 326 of 375 register name: su.rxufc register description: mac mmc receive unicast frame counter register address: 01c4h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01c4h: rxufc[31] rxufc[30] rxufc[29] rxufc[28] rxufc[27] rxufc[26] rxufc[25] rxufc[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01c5h: rxufc[23] rxufc[22] rxufc[21] rxufc[20] rxufc[19] rxufc[18] rxufc[17] rxufc[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01c6h: rxufc[15] rxufc[14] rxufc[13] rxufc[12] rxufc[11] rxufc[10] rxufc[9] rxufc[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01c7h: rxufc[7] rxufc[6] rxufc[5] rxufc[4] rxufc[3] rxufc[2] rxufc[1] rxufc[0] bits 1-31: receive unicast frame counter (rxufc[31:0]) ? contains the number of good unicast frames received. register name: su.rxlnerr register description: mac mmc receive length error counter register address: 01c8h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01c8h: rxlnerr[31] rxlnerr[30] rxlnerr[ 29] rxlnerr[28] rxlnerr[27] rxln err[26] rxlnerr[25] rxlnerr[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01c9h: rxlnerr[23] rxlnerr[22] rxlnerr[ 21] rxlnerr[20] rxlnerr[19] rxln err[18] rxlnerr[17] rxlnerr[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01cah: rxlnerr[15] rxlnerr[14] rxlnerr[ 13] rxlnerr[12] rxlnerr[11] rxln err[10] rxlnerr[9] rxlnerr[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01cbh: rxlnerr[7] rxlnerr[6] rxlnerr[5] rxlnerr[4] rxlnerr[3] rxlnerr[2] rxlnerr[1] rxlnerr[0] bits 1-31: receive length error counter (rxlnerr[31:0]) ? contains the number of frames received with length errors.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 327 of 375 register name: su.rxrange register description: mac mmc receive out of range counter register address: 01cch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01cch: rxrange[31] rxrange[30] rxrange[29] rxrange[28] rxrange[27] rx range[26] rxrange[25] rxrange[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01cdh: rxrange[23] rxrange[22] rxrange[21] rxrange[20] rxrange[19] rx range[18] rxrange[17] rxrange[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01ceh: rxrange[15] rxrange[14] rxrange[13] rxrange[12] rxrange[11] rx range[10] rxrange[9] rxrange[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01cfh: rxrange[7] rxrange[6] rxrange[5] rxrange[4] rxrange[3] rxrange[2] rxrange[1] rxrange[0] bits 1-31: receive out of range counter (rxrange[31:0]) ? contains the number of frames received with an invalid ethernet length/type field. register name: su.rxpause register description: mac mmc receive pause frame counter register address: 01d0h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01d0h: rxpause[31] rxpause[30] rxpause[29] rxpause[28] rxpause[27] rxpause[26] rxpause[25] rxpause[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01d1h: rxpause[23] rxpause[22] rxpause[21] rxpause[20] rxpause[19] rxpause[18] rxpause[17] rxpause[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01d2h: rxpause[15] rxpause[14] rxpause[13] rxpause[12] rxpause[11] rxpause[10] rxpause[9] rxpause[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01d3h: rxpause[7] rxpause[6] rxpause[5] rxpause[4] rxpause[3] rxpause[2] rxpause[1] rxpause[0] bits 1-31: receive pause fr ame counter (rxpause[31:0]) ? contains the number of good pause frames received.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 328 of 375 register name: su.rxovfl register description: mac mmc receive overflow counter register address: 01d4h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01d4h: rxovfl[31] rxovfl[30] rxovfl[29] rxovfl[28] rxovfl[27] rxovfl[26] rxovfl[25] rxovfl[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01d5h: rxovfl[23] rxovfl[22] rxovfl[21] rxovfl[20] rxovfl[19] rxovfl[18] rxovfl[17] rxovfl[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01d6h: rxovfl[15] rxovfl[14] rxovfl[13] rxovfl[12] rxovfl[11] rxovfl[10] rxovfl[9] rxovfl[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01d7h: rxovfl[7] rxovfl[6] rxovfl[5] rxovfl[4] rxovfl[3] rxovfl[2] rxovfl[1] rxovfl[0] bits 1-31: receive overflow counter (rxovfl[31:0]) ? contains the number of frames discarded due to a receive fifo overflow. register name: su.rxvlan register description: mac mmc receive vlan frame counter register address: 01d8h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01d8h: rxvlan[31] rxvlan[30] rxvlan[29] rxvlan[28] rxvlan[27] rxvlan[26] rxvlan[25] rxvlan[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01d9h: rxvlan[23] rxvlan[22] rxvlan[21] rxvlan[20] rxvlan[19] rxvlan[18] rxvlan[17] rxvlan[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01dah: rxvlan[15] rxvlan[14] rxvlan[13] rxvlan[12] rxvlan[11] rxvlan[10] rxvlan[9] rxvlan[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01dbh: rxvlan[7] rxvlan[6] rxvlan[5] rxvlan[4] rxvlan[3] rxvlan[2] rxvlan[1] rxvlan[0] bits 1-31: receive vlan frame counter (rxvlan[31:0]) ? contains the number of good and bad vlan frames received.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 329 of 375 register name: su.rxwdog register description: mac mmc receive watchdog error counter register address: 01dch (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 01dch: rxwdog[31] rxwdog[30] rxwdog[29] rxwdog[28] rxwdog[27] rxwdog[26] rxwdog[25] rxwdog[24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 01ddh: rxwdog[23] rxwdog[22] rxwdog[21] rxwdog[20] rxwdog[19] rxwdog[18] rxwdog[17] rxwdog[16] bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 01deh: rxwdog[15] rxwdog[14] rxwdog[13] rxwdog[12] rxwdog[11] rxwdog[10] rxwdog[9] rxwdog[8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01dfh: rxwdog[7] rxwdog[6] rxwdog[5] rxwdog[4] rxwdog[3] rxwdog[2] rxwdog[1] rxwdog[0] bits 1-31: receive watchdog error counter (rxwdog[31:0]) ? contains the number of frames discarded due to a receive watchdog timer error. note ? the su.rxwdog register may be unnecessary and thus may be removed. register name: su.macmcr register description: mac miscellaneous control register register address: 1018h (indirect) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 1018h: - - - - - - - - bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 1019h: - - - ftf - - - - bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 101ah: - - - - - - - - bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 101bh: - - - - - - - - bit 20: flush transmit fifo (ftf) when this bit is written to 1, the mac tr ansmit fifo is reset and cleared. this bit automatically resets to zero when the reset operati on is complete. transmission should be disabled during the flush transmit fifo operation. typically, the user will want to flush the transmit fifo prior to enabling transmission to avoid transmitting possible frame fr agments that may be in the fifo.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 330 of 375 11. functional timing 11.1 functional spi interface timing note: the transmit and receive order of the address and data bits are selected by the spi_swap pin. the r/w (read/write) msb bit and b (burst) lsb bit positi on is not affected by the spi_swap pin setting. 11.1.1 spi transmission format and cpha polarity when spi_cpha = 0, cs may be de-asserted between accesses. an access is defined as one or two control bytes followed by a data byte. cs cannot be de-asserted between the control bytes, or between the last control byte and the data byte. when spi_cpha = 0, cs may also remain asserted between accesses. if it remains asserted and the burst bit is set, no additional control bytes are expected after the first control byte(s) and data are transferred. if the burst bit is set, the address will be incremented for each additional byte of data transferred until cs is de-asserted. if cs remains asserted and the burst bit is not set, a control byte(s) is expected following the data byte, and the address for the next access will be received from that. anytime cs is de-asserted, the burst access is terminated. when spi_cpha = 1, cs may remain asserted for more than one access without being toggled high and then low again between accesses. if the burst bit is set, the addr ess should increment and no additional control bytes are expected. if the burst bit is not set, each data byte will be followed by the control byte(s) for the next access. additionally, cs may also be de-asserted between accesses when spi_cpha =1. in the case, any burst access is terminated, and the next byte received when cs is re-asserted will be a control byte. the following diagrams describe the functionality of t he spi port for the four combinations of spi_cpol and spi_cpha. they indicate the clock edge that samples the data and the level of the clock during no-transfer events (high or low). since the spi port acts as a slave device, the master device provides the clock. the user must configure the spi_cpol and spi_cpha pins to describe whic h type of clock that the ma ster device is providing. note that due to the address space of the device, the unused bits a13, a 12, and a11 should always be zero. figure 11-1. spi serial port access for read mode, spi_cpol=0, spi_cpha = 0 1 a7 a13 a12 a11 a10 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb lsb msb sck cs* mosi miso b a6 a5 a4 a3 a2 a1 lsb msb a0 figure 11-2. spi serial port access fo r read mode, spi_cpol = 1, spi_cpha = 0 sck cs* 1 a7 a13 a12 a11 a10 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb lsb msb mosi miso b a6 a5 a4 a3 a2 a1 lsb msb a0 spi_cl k cs spi_mosi spi_miso spi_cl k cs spi_mosi spi_miso
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 331 of 375 figure 11-3. spi serial port access fo r read mode, spi_cpol = 0, spi_cpha = 1 sck cs* 1 a7 a13 a12 a11 a10 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb lsb msb mosi miso b a6 a5 a4 a3 a2 a1 lsb msb a0 figure 11-4. spi serial port access fo r read mode, spi_cpol = 1, spi_cpha = 1 sck cs* 1 a7 a13 a12 a11 a10 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 lsb msb lsb msb mosi miso b a6 a5 a4 a3 a2 a1 lsb msb a0 figure 11-5. spi serial port access for write mode, spi_cpol = 0, spi_cpha = 0 0 a13 lsb msb sck cs* mosi miso d7 d6 d5 d4 d3 d2 d1 d0 lsb msb a4 a3 a2 a1 a0 lsb msb a12a11a10a9a8a7a6a5 b figure 11-6. spi serial port access for write mode, spi_cpol = 1, spi_cpha = 0 sck cs* 0 a13 lsb msb mosi miso d7 d6 d5 d4 d3 d2 d1 d0 lsb msb a4 a3 a2 a1 a0 lsb msb a12a11a10a9a8a7a6a5 b spi_clk cs spi_mosi spi_miso spi_clk cs spi_mosi spi_miso spi_clk cs spi_mosi spi_miso spi_clk cs spi_mosi spi_miso
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 332 of 375 figure 11-7. spi serial port access for write mode, spi_cpol = 0, spi_cpha = 1 sck cs* 0 a13 lsb msb mosi miso d7 d6 d5 d4 d3 d2 d1 d0 lsb msb a4 a3 a2 a1 a0 lsb msb a12a11a10a9a8a7a6a5 b figure 11-8. spi serial port access for write mode, spi_cpol = 1, spi_cpha = 1 sck cs* 0 a13 lsb msb mosi miso d7 d6 d5 d4 d3 d2 d1 d0 lsb msb a4 a3 a2 a1 a0 lsb msb a12a11a10a9a8a7a6a5 b spi_clk cs spi_mosi spi_miso spi_cl k cs spi_mosi spi_miso
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 333 of 375 11.2 functional serial interface timing the serial interface provides flexible timing to in terconnect with a wide variety of serial devices. figure 11-9 shows the basic functional timing relationship for the transmit se rial port interface. tclk may be gapped during framing overhead positions or to support fractional t1/e1/t3/e3, as shown in figure 11-11. the device provides the tsync signal as a frame or byte boundary indication to an external interface. tsync is normally active high on the first bit of the multiframe, but can be programmed to occur up to three cycles early, as shown in figure 11-12. tsync is minimally one pulse wide, but may be active for multiple clock cycles. figure 11-9. transmit serial port interface, without vcat tsync tdata tclk msb encapsulated ethernet data msb encapsulated ethernet data msb encapsulated ethernet data figure 11-10. transmit serial port interface with vcat tsync tdata tclk msb vcat oh encapsulated ethernet data msb encapsulated ethernet data msb figure 11-11. transmit serial port interface, with gapped clock tsync tdata tclk msb encapsulated ethernet data msb encapsulated ethernet msb encapsulated ethernet data lsb.....
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 334 of 375 the figure below demonstrates the ts ync pulse configured to arrive 2 cl ock cycles before the byte boundary through the use of the li.tcr register. figure 11-12. transmit serial port interf ace with vcat, early tsync (2 cycles) tsync tdata tclk msb vcat oh encapsulated ethernet data msb msb encapsulated ethernet figure 11-13 shows the basic functional timing relationshi p for the receive serial port interface. rclk may be gapped during framing overhead positions or to support fractional t1/e1/t3/e3, as shown in figure 11-15. the rsync signal must be provided to the device as a fr ame, multiframe, or byte boundary indication. vcat applications require a multiframe boundary. the expected position of the rsync pulse is not programmable, and must be provided as indicated. note that the first clock after the rsync will sample the lsb of the last byte of the previous frame. figure 11-13. receive serial port interface, without vcat, rising edge sampling rsync rdata rclk msb encapsulated ethernet data msb encapsulated ethernet data msb encapsulated ethernet data lsb figure 11-14. receive serial port interface with vcat, rising edge sampling rsync rdata rclk msb encapsulated ethernet data msb encapsulated ethernet data msb vcat oh lsb figure 11-15. receive serial port interface with gapped clock (t1) rsync rdata rclk msb encapsulated ethernet data msb encapsulated ethernet msb encapsulated ethernet data lsb fbit
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 335 of 375 11.3 voice port functional timing diagrams figure 11-16. transmit voice port interface with pcm octets tdata(o) tclk(i) tsync(i) lsb msb pcm octet 2 123456789 15 10 11 12 13 14 16 17 18 19 20 21 22 23 24 tvdata(i) pcm octet 1(prev frame) ethernet data 1 pcm octet 1 pcm octet 2 tvclk(i) tvsync(i) tvden(i) figure 11-17 shows the receive serial port timing relati onship when the data stream contains pcm octets. this example shows two pcm octets being demuxed from t he ethernet data. rvsync is minimum one clock period wide, but may be high multiple clock periods. note t hat the pcm octets output on rvdata are buffered for one rvsync period, i.e. the pcm octets are delayed one frame. voice data may be output at any point between frame syncs, output when rvden is low. figure 11-17. receive voice port interface with pcm octets rdata(i) rclk(i) rsync(i) lsb msb pcm octet 2 123456789 15 10 11 12 13 14 16 17 18 19 20 21 22 23 24 rvclk(i) rvsync(i) rvdata(o) pcm octet 1 ethernet data 1 pcm octet 1(prev frame) pcm octet 2 rvden(i)
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 336 of 375 11.4 mii/rmii and gmii interfaces in gmii mode, tx_en is high with the first bit of the preamble. for 10mbps operation, the data bit outputs are updated every 10 clocks . figure 11-18. gmii transmit interface functional timing txd[1:0 ] tx_e n ref_clk p r e a m b l e f c s gmii receive data on rxd[1:0] is expec ted to be synchronous with the risi ng edge of ______. the data is only valid if rx_crs is high. the external phy asyn chronously drives rx_crs low during carrier loss. figure 11-19. gmii receive interface functional timing rxd[1:0] rx_crs ref_clk p r e a m b l e f c s
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 337 of 375 each mii interface transmit port has its own tx_clk and data interface. the data txd [3:0] operates synchronously with tx_clk. the lsb is presented firs t. tx_clk should be 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. tx_en is valid at the same time as the first byte of the preamble. in dte mode tx_clk is input from the external phy. in dce mode, the device provides tx_clk, derived from an external reference (sysclki). in half-duplex (dte) mode, the device supports rx_crs and col signals. rx_crs is active when the phy detects transmit or receive activity. if there is a collisi on as indicated by the col inpu t, the device will replace the data nibbles with jam nibbles. after a ?random? time interval , the frame is retransmitted. the mac will try to send the frame a maximum of 16 times. the jam sequence consists of 55555555h. note that the col signal and rx_crs can be asynchronous to the tx_clk and are only valid in half duplex mode. figure 11-20. mii transmit functional timing txd[3:0] tx_en tx_clk p r e a e m b l e f c s figure 11-21. mii transmit half duplex with a collision functional timing txd[3:0] tx_en tx_clk p r e a m b l e j j j j j j j j rx_crs col receive data (rxd[3:0]) is clocked from the external phy synchronously with rx_clk. the rx_clk signal is 2.5mhz for 10mbps operation and 25mhz for 100mbps oper ation. rx_dv is asserted by the phy from the first nibble of the preamble in 100mbps operation or first ni bble of sfd for 10mbps operati on. the data on rxd[3:0] is not accepted by the mac if rx_dv is low or rx_err is high (in dte mode). rx_err should be tied low when in dce mode. figure 11-22. mii receive functional timing rxd[3:0] rx_clk p r e a e m b l e f c s rx_crs
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 338 of 375 in rmii mode, tx_en is high with the first bit of the preamble. the txd[1:0] is synchronous with the 50mhz ref_clk. for 10mbps operation, the da ta bit outputs are updated every 10 clocks . figure 11-23. rmii transmit interface functional timing txd[1:0] tx_en ref_clk p r e a m b l e f c s rmii receive data on rxd[1:0] is expe cted to be synchronous with the rising edge of the 50mhz ref_clk. the data is only valid if rx_crs is high. the external phy asynchronously drives rx_crs low during carrier loss. figure 11-24. rmii receive interface functional timing rxd[1:0] rx_crs ref_clk p r e a m b l e f c s
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 339 of 375 12. operating parameters absolute maximum ratings voltage range on any lead with respect to vss (except vdd) ...............................?0.5v to +5.5v supply voltage range (vdd3.3) with respect to vss ............................................ ?0.3v to +3.6v supply voltage range (vdd1.8) with respect to vss ............................................ ?0.3v to +2.0v ambient operating temperat ure range* ................................................................... ?40oc to +85oc junction operating temperatur e range ................................................................... ?40oc to +125oc storage temperatur e .................................................................................................?55oc to + 125oc soldering temperat ure .............................................................................................see j-std-02 0 specification these are stress ratings only and functional operation of the device at these or an y other conditions beyond those indicated in the operation sections of this specification is not im plied. exposure to absolute maximum rating co nditions for extended periods of time can affect reliability. * ambient operating temperature range is assuming the device is mounted on a jedec standard test board in a convection cooled jed ec test enclosure. note: the ?typ? values listed in this document are not production tested. note: all a/c timing parameters are guaranteed by design. table 12-1. recommended dc operating conditions (vdd3.3 = 3.3v 5%,vdd2.5 = 2.5 5%, vdd1.8 = 1.8 5%, t j = -40c to +85c.) parameter symbol conditions min typ max units logic 1 (pins other than sdram) v ih 2.00 5.5 v logic 0 (pins other than sdram) v il -0.30 +0.80 v logic 1, ddr sdram interface v ihddr vref + 0.31 2.625 v logic 0, ddr sdram interface v ilddr -0.30 vref ? 0.31 v supply (vdd3.3) 5% v dd3.3 3.135 3.3 3.465 v supply (vdd2.5) 5% v dd2.5 2.375 2.5 2.625 v supply (vddq) 5% v ddq 2.375 2.5 2.625 v supply (vdd1.8) 5% v dd1.8 1.71 1.8 1.89 v supply (avdd) 5% a vdd 1.71 1.8 1.89 v vref ddr voltage reference v vref 1.1875 1.3125 v
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 340 of 375 table 12-2. dc electrical characteristics (t j = -40c to +85c.) parameter symbol conditions min typ max units i/o supply current (vdd3.3 = 3.465v) i ddio notes 1, 2 30 50 ma core supply current (vdd1.8 = 1.89) i ddcore notes 1, 2 260 300 ma avdd 1.8v supply current i avdd notes 1, 2 5 10 ma vddq 2.5v supply current i vddq notes 1, 2 120 150 ma power-down i/o current i pdio note 3 1 ma power-down core current i pdcore note 3 1 ma power-down avdd current i pdavdd note 3 5 ma power-down vddq current i pdvddq note 3 1 ma lead capacitance c io 7 pf input leakage i il -10 +10 a input leakage (pins with internal pull-up) i ilp -100 -10 a output leakage (when hi-z) i lo -10 +10 a output voltage (i oh = -4.0ma) v oh 4 ma outputs 2.4 v output voltage (i ol = +4.0ma) v ol 4 ma outputs 0.4 v output voltage (i oh = -8.0ma) v oh 8 ma outputs 2.4 v output voltage (i ol = +12.0ma) v ol 12 ma outputs 0.4 v output voltage ddr sdram (i oh = -8.1ma) v ohddr ddr sdram outputs 1.9 v output voltage ddr sdram (i ol = +8.1ma) v olddr ddr sdram outputs 0.4 v note 1: typical total power consumption for the DS33X162 at 400mbps is approximately 1w. note 2: all outputs loaded with rated capacitance; all inputs betwe en vdd and vss; inputs with pullups connected to vdd. note 3: all disable and power-down bits set, rst held low, outputs not loaded.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 341 of 375 12.1 thermal characteristics table 12-3. thermal characteristics parameter min typ max notes ambient temperature -40 c +85 c 1 junction temperature +125 c theta-ja ( ja ) in still air for 256-ball csbga (17mm) 2 +29.9 c/w 2 theta-ja ( ja ) in still air for 144-ball csbga (10mm) 2 +47.1 c/w 2 note 1: the package is mounted on a four-layer jedec standard test board. note 2: theta-ja ( ja ) is the junction to ambient thermal resistance, when the package is mounted on a four-layer jedec standard test board.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 342 of 375 12.2 transmit and receive gmii interface table 12-4. transmit gmii interface 1000mbps parameter symbol min typ max units gtx_clk, rx_clk period t1 7.5 8 8.5 ns gtx_clk frequency 1/t1 125 - 100ppm 125 125 + 100ppm mhz gtx_clk, rx_clk high time t3 2.5 ns gtx_clk, rx_clk low time t2 2.5 ns gtx_clk to txd, tx_enn output delay t4 0.5 5.0 ns figure 12-1. transmit gmii interface timing gtx_clk txd[1:0]n tx_enn t4 t4 t2 t3 t1
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 343 of 375 table 12-5. receive gmii interface 1000mbps parameter symbol min typ max units rx_clk period t5 7.5 ns rx_clk frequency 1/t5 125 mhz rx_clk high period t6 2.5 ns rx_clk low period t7 2.5 ns rxd, rx_dv to rx_clk setup time t8 2.0 ns rx_clk to rxd, rx_dv hold time t9 0.0 ns figure 12-2. receive gmii interface timing t8 t9 rx_clkn rxd[3:0]n rx_dvn t8 t9 t5 t6 t7
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 344 of 375 12.3 transmit and receive mii interface table 12-6. transmit mii interface 10mbps 100mbps parameter symbol min typ max min typ max units tx_clk period t1 400 40 ns tx_clk low time t2 140 260 14 26 ns tx_clk high time t3 140 260 14 26 ns tx_clk to txd, tx_en delay t4 0 20 0 20 ns figure 12-3. transmit mii interface timing tx_clkn txd[3:0]n tx_enn t4 t4 t2 t3 t1
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 345 of 375 table 12-7. receive mii interface 10mbps 100mbps parameter symbol min typ max min typ max units rx_clk period t5 400 40 ns rx_clk low time t6 140 260 14 26 ns rx_clk high time t7 140 260 14 26 ns rxd, rx_dv to rx_clk setup time t8 5 5 20 ns rx_clk to rxd, rx_dv hold time t9 5 5 ns figure 12-4. receive mii interface timing t8 t9 rx_clkn rxd[3:0]n rx_dvn t8 t9 t5 t6 t7
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 346 of 375 12.4 transmit and receive rmii interface table 12-8. transmit rmii interface 10mbps 100mbps parameter symbol min typ max min typ max units ref_clk frequency 50mhz 50ppm 50mhz 50ppm ref_clk period t1 20 20 ns ref_clk low time t2 7 13 7 13 ns ref_clk high time t3 7 13 7 13 ns ref_clk to txd, tx_en delay t4 3 10 3 10 ns figure 12-5. transmit rmii interface timing ref_clk txd[1:0] tx_en t4 t4 t2 t3 t1
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 347 of 375 table 12-9. receive rmii interface 10mbps 100mbps parameter symbol min typ max min typ max units ref_clk frequency 50mhz 50ppm 50mhz 50ppm mhz ref_clk period t1 20 20 ns ref_clk low time t2 7 13 7 13 ns ref_clk high time t3 7 13 7 13 ns rxd, rx_crs to ref_clk setup time t8 5 5 ns ref_clk to rxd, rx_crs hold time t9 5 5 ns figure 12-6. receive rmii interface timing t8 t9 ref_clk rxd[3:0] rx_crs t8 t9 t5 t6 t7
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 348 of 375 12.5 mdio interface table 12-10. mdio interface parameter symbol min typ max units mdc frequency 2.016 2.5 mhz mdc period t1 400 496 ns mdc low time t2 160 ns mdc high time t3 160 ns mdc to mdio output delay t4 0 20 ns mdio input setup time t5 10 ns mdio input hold time t6 0 ns figure 12-7. mdio interface timing mdc mdio t4 mdc t2 t3 t1 mdio t5 t6
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 349 of 375 12.6 transmit and receive wan interface table 12-11. transmit wan interface parameter symbol min typ max units tclk frequency 52 mhz tclk period t1 19.2 1000 ns tclk low time t2 8 550 ns tclk high time t3 8 550 ns tclk to tdata output delay t4 11 ns tsync setup time t5 7 ns tsync hold time t6 7 ns figure 12-8. transmit wan timing (noninverted tclk) tclkn t2 t3 t1 tdatan t4 tsyncn t5 t6
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 350 of 375 table 12-12. receive wan interface parameter symbol min typ max units rclk frequency 52 mhz rclk period t1 19.2 1000 ns rclk low time t2 8 1000 ns rclk high time t3 8 1000 ns rdatan setup time t4 7 ns rsyncn setup time t4 7 ns rdatan hold time t5 2 ns rsyncn hold time t5 2 ns figure 12-9. receive wan ti ming (noninverted rclk) rclkn t2 t3 t1 rdatan t4 t5 t4 t5 rsyncn t4 t5
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 351 of 375 12.7 transmit and receive voice port interface table 12-13. transmit voice port interface parameter symbol min typ max units tvclk frequency 1/t1 16.384 mhz tvclk clock duty cycle (high/low) t3/t2 40 50 60 % tvclk rise or fall times (20% to 80%) 4 ns tvdata, tvden, tvsync to tvclk setup time t4 6 ns tvclk to tvdata, tvden, tvsync hold time t5 0 ns figure 12-10. transmit voice port interface timing tvclk t2 t3 t1 tvdata tvden t4 t5 t4 t5 tvsync t4 t5
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 352 of 375 table 12-14. receive voice port interface parameter symbol min typ max units rvclk frequency 1/t1 16.384 mhz rvclk clock duty cycle (high/low) t3/t2 40 50 60 % rvclk rise or fall times (20% to 80%) 4 ns rvden, rvsync to rvclk setup time t5 6 ns rvclk to rvden, rvsync hold time t6 0 ns rvclk to rvdata output delay t4 2 10 ns figure 12-11. receive voice port interface timing rvclk t2 t3 t1 rvdata t4 rvsync t5 t6 rvden
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 353 of 375 12.8 ddr sdram interface table 12-15. ddr sdram interface parameter symbol min typ max units sd_clk output period t1 7.5 8.5 ns sd_clk output high period t2 3.6 4.4 ns sd_clk output low period t3 3.6 4.4 ns address and control output hold time t4 3 5 ns sdata setup to sd_udqs, sd_ldqs t5 0.8 ns sdata output hold to sd_udqs, sd_ldqs t6 0.8 ns sd_udqs, sd_ldqs write preamble t7 6 10 ns sd_udqs, sd_ldqs write postamble t8 3.2 4.8 ns sd_udqs, sd_ldqs to sd_udm, sd_ldm hold time t9 1 ns sd_udm, sd_ldm to sd_udqs, sd_ldqs setup time t10 1 ns sd_udqs, sd_ldqs to sdata (read) t11 -1 +1 ns sd_clk to sd_ldqs, sd_udqs (read) t12 -1 +1 ns sd_ldqs, sd_udqs high pulse width t13 3.4 4.5 ns sd_ldqs, sd_udqs low pulse width t14 3.4 4.5 ns
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 354 of 375 figure 12-12. ddr sdram interface timing sd_clk sd_clk write t4 address / control t5 t7 t8 t9 sdata sd_udqs sd_ldqs t1 p0 p1 p2 p3 read sdata sd_udqs sd_ldqs sd_udm sd_ldm t6 t10 t11 t12 t2 t3 sd_clk sd_clk t14 t13
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 355 of 375 12.9 ac characteristics?microprocessor bus interface timing table 12-16. parallel microprocessor bus (v dd = 3.3v 5%, t a = -40 c to +85 c.) parameter symbol min typ max units setup time for a[10:0] valid to either rd , or wr active t1 10 ns setup time for cs active to either rd , or wr active t2 0 ns delay time from either rd or ds active to data[7:0] valid t3 75 ns hold time from either rd or wr inactive to cs inactive t4 0 ns hold time from cs or rd or ds inactive to data[7:0] tri-state t5 2 20 ns wait time from wr active to latch data t6 80 ns data setup time to wr inactive t7 10 ns data hold time from wr inactive t8 2 ns address hold from wr inactive t9 0 ns write access to subsequent write/read access delay time t10 80 ns
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 356 of 375 figure 12-13. intel bus read timing (mode = 0) t2 t3 address valid data valid t4 t9 t5 t10 addr[12:0] data[7:0] cs rd wr t1 figure 12-14. intel bus write timing (mode = 0) t2 t6 address valid t4 t9 t10 addr[12:0] data[7:0] cs rd wr t7 t8 t1
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 357 of 375 figure 12-15. motorola bus read timing (mode = 1) t2 t3 address valid data valid t4 t9 t5 t10 addr[12:0] data[7:0] cs ds r w t1 figure 12-16. motorola bus write timing (mode = 1) t2 t6 address valid t4 t9 t10 addr[12:0] data[7:0] cs r w ds t7 t8 t1
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 358 of 375 table 12-17. multiplexed microprocessor bus parameter symbol min typ max units input rise/fall times 20 ns address valid to wr , rd , or ds active t 1 10 ns cs setup to ds, wr , or rd active t 2 0 ns output data delay time from ds or rd t 3 75 ns ds, wr , or rd inactive to cs inactive t 4 0 ns data hold on read t 5 2 20 ns data setup to wr , or ds active t 7 10 ns data hold on write t 8 2 ns ale fall to ds, wr , or rd active t 9 2 ns ds, wr , or rd inactive to ds, wr , or rd active t 10 80 ns address valid to ale active t 11 10 ns
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 359 of 375 figure 12-17. multiplexed intel bus read timing (mode = 0) t2 t3 address valid data valid t4 t5 t10 addr[12:0] data[7:0] cs rd wr t1 ale t11 t9 figure 12-18. multiplexed intel bus write timing (mode = 0) t2 t3 address valid data valid t4 t8 t10 addr[12:0] data[7:0] cs wr rd t1 ale t11 t7 t9
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 360 of 375 figure 12-19. multiplexed motorola bus read timing (mode = 1) t2 t3 address valid data valid t4 t5 t10 addr[12:0] data[7:0] cs ds r w t1 ale t11 t9 figure 12-20. multiplexed motorola bus write timing (mode = 1) t2 t3 address valid data valid t4 t8 t10 addr[12:0] data[7:0] cs ds r w ale t11 t7 t1 t9
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 361 of 375 table 12-18. spi microprocessor bus mode symbol (1) characteristic (2) min max units operating frequency 10 mhz t1 cycle time 100 ? ns t2 enable lead time 15 ? ns t3 enable lag time 15 ? ns t4 clock (spi_clk) high time 50 ? ns t5 clock (spi_clk) low time 50 ? ns t6 data setup time (input) 5 ? ns t7 data hold time (input) 15 ? ns t8 disable time (3) ? 25 ns t9 data hold time 5 ? ns note 1: symbols refer to dimensions in the following figure. note 2: 100 pf load on all spi pins. note 3: hold time to high-impedance state. figure 12-21. spi interface timing diagram cs spi_cl k msb bits 6 - 1 lsb note 2 spi_miso msb bit 15 bits 13 - 0 spi_mosi t 9 t 6 t 7 t 2 t 1 t 4 t 5 t 8 t 3
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 362 of 375 12.10 jtag interface table 12-19. jtag interface (vdd = 3.3v 5%, t a = -40 c to +85 c.) parameter symbol min typ max units jtclk clock period t1 1000 ns jtclk clock high:low time (note 1) t2 : t3 50 500 ns jtclk to jtdi, jtms setup time t4 2 ns jtclk to jtdi, jtms hold time t5 2 ns jtclk to jtdo delay t6 2 50 ns jtclk to jtdo hiz delay t7 2 50 ns jtrst width low time t8 100 ns note 1: clock can be stopped high or low. figure 12-22. jtag interface timing jtcl k t1 jtd0 t4 t5 t2 t3 t7 jtdi, jtms, j trs t t6 jtrst t8
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 363 of 375 13. jtag information the device supports the st andard instruction codes sample:preloa d, bypass, and extest. optional public instructions included are hi ghz, clamp, and idcode. see table 13-1 . the device contains the following as required by ieee 1149.1 standar d test access port and b oundary scan architecture. test access port (tap) tap controller instruction register bypass register boundary scan register device identification register the test access port has the necessa ry interface pins; jtrst, jtclk, jtms, jtdi, and jtdo. see the pin descriptions for details. refer to ieee 1149.1-1990, ieee 1149. 1a-1993, and ieee 1149.1b- 1994 for details about the boundary scan architecture and the test access port. figure 13-1. jtag functional block diagram jtdi jtms jtclk j trst jtdo test access port controller v dd v dd v dd boundry scan register bypass register instruction register identification register mux select tri-state 10k 10k 10k
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 364 of 375 13.1 jtag tap controller state machine description this section covers the details on the operation of the test access port (tap) controller state machine. the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk. 13.1.1 tap controller state machine the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk. see figure 13-2 for a diagram of the state machine operation. 13.1.1.1test-logic-reset upon power-up, the tap controller is in the test-logic-reset state. the instruction r egister will contain the idcode instruction. all system logic of the device will operate normally. 13.1.1.2run-test-idle the run-test-idle is used between scan operations or duri ng specific tests. the instruction register and test registers will remain idle. 13.1.1.3select-dr-scan all test registers retain their previous state. with jtms low, a rising edge of jtclk moves the controller into the capture-dr state and will initiate a scan sequence. jtms high during a rising edge on jtclk moves the controller to the select-ir-scan state. 13.1.1.4capture-dr data may be parallel-loaded into the test data registers sele cted by the current instruct ion. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. on the rising edge of jtclk, the controller w ill go to the shift-dr state if jtms is low or it will go to the exit1-dr state if jtms is high. 13.1.1.5shift-dr the test data register selected by t he current instruction is connected between jtdi and jtdo and will shift data one stage towards its serial output on each rising edge of jt clk. if a test register selected by the current instruction is not placed in the serial pat h, it will maintain its previous state. 13.1.1.6exit1-dr while in this state, a rising edge on jtclk will put the controller in the up date-dr state, which terminates the scanning process, if jtms is high. a rising edge on jtcl k with jtms low will put the controller in the pause- dr state. 13.1.1.7pause-dr shifting of the test registers is halted while in this state. all test registers selected by the current instruction will retain their previous state. the controller will remain in this state while jtms is low. a rising edge on jtclk with jtms high will put the contro ller in the exit2-dr state. 13.1.1.8exit2-dr a rising edge on jtclk with jtms high while in this state will put the controller in the update-dr state and terminate the scanning process. a rising edge on jtcl k with jtms low will enter the shift-dr state.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 365 of 375 13.1.1.9update-dr a falling edge on jtclk while in the up date-dr state will latch the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output due to changes in the shift register. 13.1.1.10 select-ir-scan all test registers retain their previous state. the instruction register will remain unchanged during this state. with jtms low, a rising edge on jtclk mo ves the controller into the capture- ir state and will initiate a scan sequence for the instruction register. jtms high duri ng a rising edge on jtclk puts the controller back into the test-logic-reset state. 13.1.1.11 capture-ir the capture-ir state is used to load the shift register in t he instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the rising edge of jtclk, the controller will enter the exit1-ir state. if jtms is low on the rising edge of jtclk, the controller will enter the shift-ir state. 13.1.1.12 shift-ir in this state, the shift register in the instruction r egister is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk towards the serial out put. the parallel register, as well as all test registers, remains at their previous states. a rising edge on jtclk wi th jtms high will move t he controller to the exit1-ir state. a rising edge on jtclk with jtms low will keep the controller in the shift-ir state while moving data one stage thorough the instruction shift register. 13.1.1.13 exit1-ir a rising edge on jtclk with jtms low w ill put the controller in the pause-ir state. if jtms is high on the rising edge of jtclk, the controller will enter the updat e-ir state and terminate the scanning process. 13.1.1.14 pause-ir shifting of the instruction shift register is halted tempor arily. with jtms high, a rising edge on jtclk will put the controller in the exit2-ir state. the c ontroller will remain in the pause-ir stat e if jtms is low during a rising edge on jtclk. 13.1.1.15 exit2-ir a rising edge on jtclk with jtms low will put the controller in the update-ir state. the controller will loop back to shift-ir if jtms is high during a rising edge of jtclk in this state. 13.1.1.16 update-ir the instruction code shifted into the instruction shift regi ster is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on jtclk with jtms held low will put the controller in the run-test-idle stat e. with jtms high, the controller will enter the select-dr-scan state.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 366 of 375 figure 13-2. tap controller state diagram 1 0 0 1 11 1 1 1 1 1 11 1 1 00 0 0 0 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 367 of 375 13.2 instruction register the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift-ir state, the instruction shift register is connected between jtdi and jtdo. while in the shift-ir state, a rising edge on jtclk with jtms low w ill shift the data one stage towards the serial output at jtdo. a rising edge on jtclk in the exit1-ir state or the ex it2-ir state with jtms high will move the controller to the update-ir state. the falling edge of that same jtclk will latch the data in the instruction shift register to the instruction parallel output. instructions supported by the device and its resp ective operational binary codes are shown in table 13-1 . table 13-1. instruction codes for ieee 1149.1 architecture instruction selected regi ster instruction codes sample:preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 highz bypass 100 idcode device identification 001 13.2.1 sample:preload this is a mandatory instruction for th e ieee 1149.1 specification. this in struction supports two functions. the digital i/os of the device can be sampled at the boundary sc an register without interferi ng with the normal operation of the device by using the capture-dr state. sample:preload also allows the device to shift data into the boundary scan register via jtdi using the shift-dr state. 13.2.2 bypass when the bypass instruction is latched into the parallel instruction register , jtdi connects to jtdo through the one-bit bypass test register. this allows data to pass from jtdi to jtdo not affecting the device?s normal operation. 13.2.3 extest this allows testing of all interconnections to the device. when the extest instruction is latched in the instruction register, the following actions occur. once enabled via the update-ir state, the parallel outputs of all digital output pins are driven. the boundary scan regi ster is connected between jtdi and jtdo. the capture-dr will sample all digital inputs into the boundary scan register. 13.2.4 clamp all digital outputs of the device will output data from t he boundary scan parallel output while connecting the bypass register between jtdi and jtdo. the outputs w ill not change during the clamp instruction. 13.2.5 highz all digital outputs of the device are placed in a high- impedance state. the bypass regi ster is conn ected between jtdi and jtdo. 13.2.6 idcode when the idcode instruction is latched into the parallel instruction register, the ident ification test register is selected. the device identification code is loaded into th e identification register on the rising edge of jtclk following entry into the capture-dr stat e. shift-dr can be used to shift the identification code out serially via jtdo. during test-logic-reset, the identification code is fo rced into the instruction register?s parallel output. the
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 368 of 375 id code will always have a 1 in the lsb position. th e next 11 bits identify the m anufacturer?s jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. 13.3 jtag id codes table 13-2. id code structure device revision id[31:28] device code id[27:12] manufacturer?s code id[11:1] required id[0] ds33xyy rev a1 0000 0000 0000 0000 0110 000 1010 0001 1 ds33xyy rev b1 0001 0000 0000 0000 0110 000 1010 0001 1 13.4 test registers ieee 1149.1 requires a minimum of two te st registers: the bypass register and the boundary scan register. an optional test register has been included in the device. this test register is the identification register and is used in conjunction with the idcode instruction and the test-logic-reset state of the tap controller. 13.4.1 boundary s can register this register contains both a shift regi ster path and a latched parallel output for all control cells and digital i/o cells and is n bits in length. 13.4.2 bypass register this is a single one-bit shift register used in conjun ction with the bypass, clamp, and highz instructions, which provides a short path between jtdi and jtdo. 13.4.3 identification register the identification register c ontains a 32-bit shift register and a 32-bit latched parallel output. this register is selected during the idcode instruction and when the t ap controller is in the test-logic-reset state.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 369 of 375 13.5 jtag functional timing this functional timing for the jtag circuits shows: ? the jtag controller starting from reset state. ? shifting out the first 4 lsb bits of the idcode. ? shifting in the bypass instruction (111) while shifting out the mandatory x01 pattern. ? shifting the tdi pin to the tdo pin through the bypass shift register. ? an asynchronous reset occurs while shifting. figure 13-3. jtag functional timing jtclk jtrst jtms jtdi jtdo (state) reset x run test idle select dr scan capture dr shift dr exit1 dr update dr select dr scan select ir scan capture ir shift ir exit1 ir update ir select dr scan capture dr shift dr test logic idle (inst) idcode bypass idcode x x x x x output pin output pin level change if in "extest" instruction mode
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 370 of 375 14. pin configuration 14.1 DS33X162/x161/x82/x81/x42/x41 pin configuration?256-ball csbga 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a jtclk sda[3] sda[10] sdcs sda[12] sras swe sd_clk sd_clk vss vddq vddq sdata[6] sdata[4] vddq vddq b jtrst sda[2] sba[1] sba[0] sda[6] sda[9] scas vdd2.5 vref sd ata[12] sdata[13] sdata[15] sdata[7] vssq sdata[2] sdata[1] c jtms sda[1] sda[0] sd_clke n sda[7] sda[11] vss vssq sdata[9] sdata[11] sdata[14] sdata[5] sd_ldqs vddq sdata[3] sdata[0] d rdata1 jtdi sda[4] sda[5] sda[8] vssq sd_udm sd_udqs sdata[8] vddq vdd1.8 sdata[10] sd_ldm vddq vssq vssq e rclk1 jtdo vdd1.8 vdd1.8 vdd2.5 vssq vdd2.5 rst vdd3.3 vdd3.3 avss vdd3.3 rx_crs1 col1 vssq sysclki f rsync1 rdata6 rdata5 rclk5 avdd vss vdd3.3 vss vss vss vss vdd1.8 rxd[1] / rxd1[1] rxd[2] / rxd1[2] mdc vss g rclk3 rsync3 rsync5 rdata3 vdd3.3 vss rclk2 rdata2 vss a8 a10 vdd1.8 mdio rxd[0] / rxd1[0] rx_dv1 rx_clk1 h rsync4 rdata4 rsync6 rclk4 vss dnc rsync2 dnc vss vss vdd1.8 vdd1.8 txd[3] / txd1[3] rxd[3] / rxd1[3] rx_err1 hiz j rclk6 rclk10 rclk9 rclk8 rclk7 dnc ale cs rd / ds wr / r w int mode txd[0] / txd1[0] rx_crs2 txd[2] / txd1[2] spi_sel k rdata7 rdata9 rdata10 rsync9 vdd3.3 d0 / spi_miso d2 / spi_clk d4 d6 / spi_cpha a0 a2 a6 a4 tx_en1 txd[1] / txd1[1] rxd[7] / rxd2[3] l rdata8 rsync8 rsync11 rdata12 rclk13 d1 / spi_mosi d3 d5 /spi_ swap a1 a3 a5 a7 a9 tx_err1 rxd[6] / rxd2[2] col2 m rsync10 rclk11 vdd1.8 rsync13 tdata5 tsync3 tclk5 vdd3.3 d7 / spi_cpol tmclk4 rx_dv2 rx_err2 vss rmii_sel tx_clk1 rxd[5] / rxd2[1] n rdata11 rclk12 rdata15 rdata16 rsync7 tdata6 tdata7 tsync7 tdata4 tdata9 tdata11 tdata15 rx_clk2 tmsync4 txd[4] / txd2[0] rxd[4] / rxd2[0] p rsync12 rdata13 rsync15 vdd3.3 tclk2 tdata3 tsync4 tsync6 tclk4 tclk6 tdata16 tdata14 dcedtes tdata13 txd[5] / txd2[1] tx_en2 r rdata14 rsync14 rclk16 vss tclk1 tsync1 tsync5 tclk3 tdata8 tclk8 tdata10 tdata12 vdd1.8 gtx_clk txd[6] / txd2[2] tx_err2 t rclk14 dnc rsync16 rclk15 vss tdata1 tdata2 tsync2 tsync8 tclk7 tmclk3 tmsync3 ref_clk vdd3.3 txd[7] / txd2[3] tx_clk2 note: shaded pins do not apply to all devices in the product family. s ee the pin listing for specific pin availability. in the high p ort count devices, the shaded input pins do not have pullup/p ulldown resistors. consider ation must be taken during board design to bias the inputs appropriately, and to float out put pins (tdata5-tdata16, tx_en2, tx_err2) if lower port count designs are to be potentially stu ffed with higher port count devices.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 371 of 375 14.2 ds33w41/ds33w11 pin configuration?256-ball csbga 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a jtclk sda[3] sda[10] sdcs sda[12] sras swe sd_clk sd_clk vss vddq vddq sdata[6] sdata[4] vddq vddq b jtrst sda[2] sba[1] sba[0] sda[6] sda[9] scas vdd2.5 vref sd ata[12] sdata[13] sdata[15] sdata[7] vssq sdata[2] sdata[1] c jtms sda[1] sda[0] sd_clke n sda[7] sda[11] vss vssq sdata[9] sdata[11] sdata[14] sdata[5] sd_ldqs vddq sdata[3] sdata[0] d rdata1 jtdi sda[4] sda[5] sda[8] vssq sd_udm sd_udqs sdata[8] vddq vdd1.8 sdata[10] sd_ldm vddq vssq vssq e rclk1 jtdo vdd1.8 vdd1.8 vdd2.5 vssq vdd2.5 rst vdd3.3 vdd3.3 avss vdd3.3 rx_crs1 col1 vssq sysclki f rsync1 rvdata rvclk rvsync avdd vss vdd3.3 vss vss vss vss vdd1.8 rxd[1] / rxd1[1] rxd[2] / rxd1[2] mdc vss g rclk3 rsync3 rvden rdata3 vdd3.3 vss rclk2 rdata2 vss a8 a10 vdd1.8 mdio rxd[0] / rxd1[0] rx_dv1 rx_clk1 h rsync4 rdata4 rclk4 vss dnc rsync2 dnc vss vss vdd1.8 vdd1.8 txd[3] / txd1[3] rxd[3] / rxd1[3] rx_err1 hiz j dnc ale cs rd / ds wr / r w int mode txd[0] / txd1[0] txd[2] / txd1[2] spi_sel k vdd3.3 d0 / spi_miso d2 / spi_clk d4 d6 / spi_cpha a0 a2 a6 a4 tx_en1 txd[1] / txd1[1] rxd[7] / rxd2[3] l d1 / spi_mosi d3 d5 /spi_ swap a1 a3 a5 a7 a9 tx_err1 rxd[6] / rxd2[2] m vdd1.8 tvdata tsync3 tvclk vdd3.3 d7 / spi_cpol vss rmii_sel tx_clk1 rxd[5] / rxd2[1] n tvden tdata4 txd[4] / txd2[0] rxd[4] / rxd2[0] p vdd3.3 tclk2 tdata3 tsync4 tclk4 dcedtes txd[5] / txd2[1] r vss tclk1 tsync1 tvsync tclk3 vdd1.8 gtx_clk txd[6] / txd2[2] t dnc rclk15 vss tdata1 tdata2 tsync2 ref_clk vdd3.3 txd[7] / txd2[3] note 1: shaded pins do not apply to the ds33w11. see the pin listing for specific pin availability. note 2: the tvden pin is an input on the ds33w41/ds33w11, and is an output pin on other devices in the product family.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 372 of 375 14.3 ds33x11 pin configuration?144-ball csbga 1 2 3 4 5 6 7 8 9 10 11 12 a vss vddq sda[0] sda[9] sdcs vss sd_clk sd_clk sdata[15] sdata[4] sdata[0] vss b vdd2.5 sda[2] sda[8] sda[11] sras vss vss sdata[10] sdata[14] sdata[5] sdata[1] vddq c sda[4] sda[6] sda[10] sba[1] swe vdd2.5 vddq sdata[8] sdata[12] sdata[7] sdata[3] avss d sda[3] sda[1] sda[12] sba[0] scas vref sd_udq s sdata[9] sdata[13] sdata[6] sdata[2] avdd e sda[5] sda[7] vss vddq sd_clken sd_ldm sd_udm sd_ldqs sdata[11] vddq vss sysclki f vdd1.8 rst vdd3.3 dnc dnc vss vss tx_en1 rx_dv1 hiz vdd3.3 vss g rclk1 jtms jtclk jtrst int vdd1.8 vdd1.8 tx_err1 rx_err1 col1 vss rx_crs1 h vdd3.3 jtdo jtdi mdio mdc vdd3.3 vdd3.3 txd[2] txd[3] rxd[2] rxd[3] vdd1.8 j rsync1 rdata1 cs spi_miso spi_swap vss vss txd[0] txd[1] rxd[0] rxd[1] rx_clk1 k vss vss dnc spi_mosi spi_cpha vss rmii_sel txd[5] txd[7] rxd[6] rxd[7] vdd3.3 l vdd1.8 dnc tdata1 spi_clk spi_cpol vss dcedtes txd[4] txd[6] rxd[4] rxd[5] tx_clk1 m vss vdd3.3 tclk1 tsync1 vdd1.8 vss vdd3.3 ref_clk vss gtx_clk vdd1.8 vss note that the parallel bus is not available in the 144-pin ds 33x11, and the spi slave port must be used for processor control.
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 373 of 375 15. package information the package drawing(s) in this data sheet may not reflect the most current specifications. the package number provided for each package is a link to the latest package outline information. for the latest package outline drawings and land patterns, go to www.maxim-ic.com/packages . 15.1 256-ball csbga, 17mm x 17mm ( 56-g6017-001 )
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 374 of 375 15.2 144-ball csbga, 10mm x 10mm ( 56-g6008-003 )
________________________________________________ ds33x 162/x161/x82/x81/x42/ x41/x11/w41/w11 rev: 063008 375 of 375 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the ci rcuitry and specifications wi thout notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2008 maxim integrated products is a registered trademark of maxim integrated products. 16. document revision history revision date description pages changed 012108 initial release (initial preliminary release 060607). ? added section 8.19.3: programmable ethernet destination address filtering . 85 corrected ar.bftoa bit names. 113, 223 corrected su.gmiia bits 10:6 names. 131, 279 corrected wnvdf bit definition (su.wem, bit 7). 164 corrected llip[2:1] bit definition (su.lim, bits 3:2). 171 clarified lp1pf[2:1] and lp1etf[2:1] bi t definitions (su.lp1c, bits 4:1). 178 clarified lp2pf[2:1] and lp2etf[2:1] bi t definitions (su.lp2c, bits 4:1). 179 corrected ar.wq1ea bits 15:8 names to co rrectly match the register bit map in table 10-2. 210 clarified wispl bit definition (ar.mqc, bit 3). 221 updated ebbys bit definition (pp.emcr, bit 8). 230 updated dbbs bit definition (pp.dmcr, bit 9). 236 clarified lm bit definition (su.maccr, bit 12). 276 050808 added pm bit definition (su.macffr, bit 0). 277 060508 removed future status from ds33w11 in the ordering information table. 1 063008 removed future status from ds33 w41, ds33x41, ds33x42, ds33x82, and ds33x161 in the ordering information table. 1

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